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AD9520-5 データシート

部品番号コンポーネント説明メーカー
AD9520-5 12 LVPECL/24 CMOS Output Clock Generator ADI
Analog Devices ADI
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GENERAL DESCRIPTION
The AD9520-51 provides a multioutput clock distribution function with subpicosecond jitter performance, along with an on-chip PLL that can be used with an external VCO.
The AD9520-5 serial interface supports both SPI and I²C ports. An in-package EEPROM, which can be programmed through the serial interface, can store user-defined register settings for power-up and chip reset.
The AD9520-5 features 12 LVPECL outputs in four groups. Any of the 1.6 GHz LVPECL outputs can be reconfigured as two 250 MHz CMOS outputs. If an application requires LVDS drivers instead of LVPECL drivers, refer to the AD9522-5.
Each group of three outputs has a divider that allows both the divide ratio (from 1 to 32) and the phase offset or coarse time delay to be set.
The AD9520-5 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. The external VCO can have an operating voltage of up to 5.5 V. A separate output driver power supply can be from 2.375 V to 3.465 V.
The AD9520-5 is specified for operation over the standard industrial range of −40°C to +85°C.

FEATURES
   Low phase noise, phase-locked loop (PLL)
      Optional external 3.3 V/5 V VCO/VCXO to 2.4 GHz
      1 differential or 2 single-ended reference inputs
      Accepts CMOS, LVDS, or LVPECL references to 250 MHz
      Accepts 16.62 MHz to 33.3 MHz crystal for reference input
      Optional reference clock doubler
      Reference monitoring capability
      Automatic/ manual reference holdover and reference
         switchover modes, with revertive switching
      Glitch-free switchover between references
      Automatic recovery from holdover
      Digital or analog lock detect, selectable
      Optional zero delay operation
   Twelve 1.6 GHz LVPECL outputs divided into 4 groups
      Each group of 3 outputs shares a 1-to-32 divider with
         phase delay
      Additive output jitter as low as 225 fs rms
      Channel-to-channel skew grouped outputs < 16 ps
      Each LVPECL output can be configured as 2 CMOS outputs
         (for fOUT ≤ 250 MHz)
   Automatic synchronization of all outputs on power-up
   Manual output synchronization available
   SPI- and I²C-compatible serial control port
   64-lead LFCSP
   Nonvolatile EEPROM stores configuration settings

APPLICATIONS
   Low jitter, low phase noise clock distribution
   Clock generation and translation for SONET, 10Ge, 10GFC,
      Synchronous Ethernet, OTU2/3/4
   Forward error correction (G.710)
   Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
   High performance wireless transceivers
   ATE and high performance instrumentation
   Broadband infrastructures

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