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RED100 データシート

部品番号コンポーネント説明メーカー
RED100 AC LINE FREQUENCY DIVIDERS LSI
LSI Corporation  LSI
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DESCRIPTION OF OPERATION:
The counter advances by one on each negative transition of the input clock pulse as long as the Enable signal is High and the Reset signal is Low. When the Enable signal is Low the input clock pulses will be inhibited and the counter will be held at the state it was in prior to bringing the Enable Low. A High Reset signal clears the counter to zero count.

FEATURES:
• Clock input pulse shaper accepts 50Hz/60Hz sine wave directly
• Fully static counter operation
• +4.5V to +15V operation (VDD - VSS)
• Low power dissipation
• High noise immunity
• Reset
• Input Enable
• 50Hz/60Hz division select input
• Output low power TTL compatible at +4.5V operation
• Square Wave Output (except for ÷ 5)
• RED x/y (DIP); RED x/y-S (SOIC) See Figure 1

 

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