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SN65DSI83 データシート

部品番号コンポーネント説明メーカー
SN65DSI83 MIPI® DSI BRIDGE TO FLATLINK™ LVDS Single Channel DSI to Single-Link LVDS Bridge TI
Texas Instruments TI
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DESCRIPTION
The SN65DSI83 DSI to FlatLink™ bridge features a single-channel MIPI® D-PHY receiver front-end configuration with 4 lanes per channel operating at 1Gbps per lane; a maximum input bandwidth of 4 Gbps. The bridge decodes MIPI® DSI 18 bpp RGB666 and 24 bpp RGB888 packets and converts the formatted video data stream to a FlatLink™ compatible LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a Single-Link LVDS with four data lanes per link.

FEATURES
• Implements MIPI® D-PHY Version 1.00.00 Physical Layer Front-End and Display Serial Interface (DSI) Version 1.02.00
• Single Channel DSI Receiver Configurable for One, Two, Three, or Four D-PHY Data Lanes Per Channel Operating up to 1 Gbps Per Lane
• Supports 18 bpp and 24 bpp DSI Video Packets with RGB666 and RGB888 Formats
• Max Resolution up to 60 fps WUXGA 1920 x 1200 at 18 bpp and 24 bpp Color with Reduced Blanking. Suitable for 60 fps 1366 x 768 / 1280 x 800 at 18 bpp and 24 bpp
• FlatLink™ Output for Single-Link LVDS
• Supports Single Channel DSI to Single-Link LVDS Operating Mode
• LVDS Output Clock Range of 25 MHz to 154MHz
• LVDS Pixel Clock May be Sourced from Free Running Continuous D-PHY Clock or External Reference Clock (REFCLK)

APPLICATIONS
• Tablet PC, Notebook PC, Netbooks
• Mobile Internet Devices

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