Freescale Semiconductor, Inc.
Timing Diagrams
IN1,
IN2,
OE
OUTA,
OUTB
50%
tPLH
90%
10%
tPHL
t VGON
11 V
VDD
VCRES
Figure 2. tPLH, tPHL, and tPZH Timing
Figure 4. Charge Pump Timing Diagram
VDDDETon 2.5 V/3.5 V
VDD
0.8 V/
1.5 V
t VDDDET
50%
90%
IM
VDDDEToff
t VDDDET
0%
(<1.0 µA)
Figure 3. Low-Voltage Detection Timing Diagram
Table 1. Truth Table
INPUT
OE
IN1A
IN2A
IN1B
IN2B
L
L
L
L
H
L
L
L
H
L
H
H
H
X
X
H = High.
L = Low.
Z = High impedance.
X = Don’t care.
OE terminal is pulled up to VDD with internal resistance.
OUT1A
OUT2A
L
H
L
Z
Z
OUTPUT
OUT1B
OUT2B
L
L
H
Z
Z
MOTOROLA ANALOG INTEGRATED CIRFCoUrITMDEoVrIeCEIDnAfoTArmation On This Product,
Go to: www.freescale.com
17529
7