Figure 1: Start/Stop Timing
SCL
SDA
START
CONDITION
CAT24AA01, CAT24AA02
STOP
CONDITION
Figure 2: Slave Address Bits
1 0 1 0 0 0 0 R/¯W¯
Figure 3: Acknowledge Timing
SCL FROM
MASTER
BUS RELEASE DELAY (TRANSMITTER)
1
8
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACK DELAY (≤ tAA)
BUS RELEASE DELAY (RECEIVER)
9
ACK SETUP (≥ tSU:DAT)
Figure 4: Bus Timing
tF
tHIGH
tR
tLOW
tLOW
SCL
tSU:STA
tHD:DAT
tHD:STA
tSU:DAT
SDA IN
SDA OUT
tAA
tDH
tSU:STO
tBUF
© Catalyst Semiconductor, Inc.
5
Characteristics subject to change without notice
Doc. No. MD-1120 Rev. B