DAC08
10.000V
MSB
LSB
B1 B2 B3 B4 B5 B6 B7 B8 10.000k⍀
IREF(+) = 2.000mA
14
IO
4
EO
2
EO
IO
B1 B2 B3 B4 B5 B6 B7 B8 EO
EO
POS. FULL RANGE
1 1 1 1 1 1 1 1 –9.920 +10.000
10.000k⍀ POS. FULL RANGE –LSB 1 1 1 1 1 1 1 0 –9.840 +9.920
ZERO-SCALE +LSB
1 0 0 0 0 0 0 1 –0.080 +0.160
ZERO-SCALE
1 0 0 0 0 0 0 0 0.000 +0.080
ZERO-SCALE –LSB
0 1 1 1 1 1 1 1 +0.080 0.000
NEG. FULL-SCALE +LSB 0 0 0 0 0 0 0 1 +9.920 –9.840
NEG. FULL-SCALE
0 0 0 0 0 0 0 0 +10.000 –9.920
Figure 10. Basic Bipolar Output Operation
VREF
10V
10k⍀
POT
LOW T.C.
4.5k⍀
14
IREF(+) 2mA
39k⍀
1V
15
APPROX
5k⍀
Figure 11. Recommended Full-Scale Adjustment Circuit
RREF
14
IO
4
R15
–VREF
IFS
–VREF
RREF
IO
2
15
NOTE
RREF SETS IFS; R15 IS FOR
BIAS CURRENT CANCELLATION.
Figure 12. Basic Negative Reference Operation
10k⍀
15V
2
10V 6
VO
5
REF01*
MSB
LSB
B1 B2 B3 B4 B5 B6 B7 B8
5.000k⍀
IO 4
5.0k⍀
V+ V– CC VLC
IO 2
5.0k⍀
+15V
OP711
POS. FULL RANGE
B1 B2 B3 B4 B5 B6 B7 B8 EO
1 1 1 1 1 1 1 1 +4.960
EO ZERO-SCALE
1 0 0 0 0 0 0 0 0.000
NEG. FULL-SCALE +1 LSB 0 0 0 0 0 0 0 1 –4.960
NEG. FULL-SCALE
0 0 0 0 0 0 0 0 –5.000
4
*OR ADR01
+15V –15V
–15V
Figure 13. Offset Binary Operation
RL
4
IO
OP711
2
IO
EO
0 TO +IFR ؋ RL
IFR
=
255
256
IREF
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC DAC),
CONNECT INVERTING INPUT OF OP AMP TO IO (PIN 2); CONNECT IO (PIN 4) TO
GROUND.
Figure 14. Positive Low Impedance Output Operation
4
IO
OP711
EO
0 TO –IFR ؋ RL
2
IO
RL
IFR
=
255
256
IREF
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC DAC),
CONNECT NONINVERTING INPUT OF OP AMP TO IO (PIN 2); CONNECT IO (PIN 4)
TO GROUND.
Figure 15. Negative Low Impedance Output Operation
REV. B
TTL, DTL
VTH = 1.4V
VLC
1
VTH = V LC 1.4V
15V CMOS
VTH = 7.6V
15V
ECL
CMOS, HTL, NMOS
V+
9.1k⍀
6.2k⍀
VLC
0.1F
13k⍀
20k⍀
2N3904
“A”
39k⍀
3k⍀
2N3904
TO PIN 1
VLC
6.2k⍀
2N3904
“A”
20k⍀
3k⍀
2N3904
TO PIN 1
VLC
R3
400A
–5.2V TEMPERATURE COMPENSATING V LC CIRCUITS
Figure 16. Interfacing with Various Logic Families
–9–