512 Kbit SPI Serial Flash
SST25VF512A
Data Sheet
CE#
SCK
SO
SI
HOLD#
THHH
THLS
THZ
THLH
THHS
TLZ
FIGURE 18: HOLD TIMING DIAGRAM
VDD
VDD Max
Chip selection is not allowed.
All commands are rejected by the device.
VDD Min
TPU-READ
TPU-WRITE
Device fully accessible
1264 F18.0
FIGURE 19: POWER-UP TIMING DIAGRAM
©2006 Silicon Storage Technology, Inc.
21
Time
1264 F19.0
S71264-02-000
1/06