3.4 UNUSED PINS TREATMENT
Pin
P00/INT4
P01/SCK
P02/SO
P03/SI
P10/INT0 to P12/INT2
P13/TI0
P20 to P22
P23/BUZ
P30 to P33
P40 to P43
P50 to P53
P60 to P63
PPO
S0 to S9
T15/S10 to T14/S11
T0 to T9
T10/PH3 to T13/PH0
XT1
XT2
RESET when there is an on-
chip power-on reset circuit
VLOAD when there is no on-
chip load resistor
Recommended Connection
Connect to VSS
Connect to VSS or VDD
Connect to VSS
Input state : Connect to VSS or VDD
Output state : Leave open
Leave open
Connect to VSS or VDD
Leave open
Connect to VDD
Connect to VSS or VDD
µPD75208
10