tm TE
CH
FUNCTIONAL BLOCK DIAGRAM
16
A0-A15
MODE
ADV
CLK
ADSC
ADSP
ADDRESS 16
14
16
REGISTER
A0 A1
BINARY
COUNTER
& LOGIC
A1'
Q1
Q0 A0'
CLR
T35L6432B
BWE
8
8
BYTE 4
BYTE 4
WRITE REGISTER
WRITE DRIVER
BW4
8
8
BYTE 3
BYTE 3
WRITE REGISTER
WRITE DRIVER
32
64K x 8 x 4
32
OUTPUT
32
DQ1
BW3
MEMORY
SENSE
BUFFERS
.
AMPS
ARRAY
.
BYTE 2
8
8
BYTE 2
.
DQ32
WRITE REGISTER
WRITE DRIVER
BW2
BYTE 1
WRITE REGISTER
8
8
BYTE 1
WRITE DRIVER
BW1
GW
ENABLE
CE
REGISTER
CE2
CE2
OE
INPUT
REGISTERS
4
Note: The Functional Block Diagram illustrates simplified device operation. See Truth Table,
pin descriptions and timing diagrams for detailed information.
Taiwan Memory Technology, Inc. reserves the right P. 2
to change products or specifications without notice.
Publication Date: JUL. 2002
Revision: A