RMWL38001 データシートの表示（PDF） - Fairchild Semiconductor
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RMWL38001 Datasheet PDF : 6 Pages
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0.0 0.293
1.25
1.476 1.7375 2.013
2.9
1.25
0.774
0.6245
0.475
0.775
0.6255
0.476
0.0
0.0
0.0
Dimensions in MM
0.645 0.895
1.895
2.645 2.9
Figure 2. Chip Layout and Bond Pad Locations
(Chip Size is 2.9mm x 1.25mm x 100µm. Back of chip is RF and DC Ground)
DRAIN SUPPLY
Vd = +4V
L
10,000pF
100pF L
100pF L
L
L
L
MMIC CHIP
RF IN
L
10,000pF
L
L 100pF
RF OUT
GROUND
(Back of Chip)
L
L
100pF
L
L
100pF
GATE SUPPLY
Vg
L = BOND WIRE INDUCTANCE
Figure 3. Recommended Application Schematic Circuit Diagram
©2004 Fairchild Semiconductor Corporation
RMWL38001 Rev. C
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