SC9256S データシートの表示（PDF） - Silan Microelectronics

部品番号

コンポーネント説明

メーカー

SC9256S

PLL FOR DTS

Silan Microelectronics 

Silan

Semiconductors

SC9256

R

S

DO

Low level

floating

High level

DO Output Timing Chart

Fig.8

VCC

R1

DO

R2 C RL

Tr1

Tr2

R3

Standard

Tr1:2SC1815

Tr2:2SK246

To VCO varactor diode

Typical low-pass filter constants

(FM band reference values)

­ C=0.33 F

¡ R1=10K

¡ R2=8.2K

¡ R3=330

¡ RL=10K

Typical Active Low-Pass Filter Circuit

Fig.9

The figures above show the DO output timing chart and a typical active low-pass filter circuit featuring a

Darlington connection between the FET and transistor.

The filter circuit shown above is just one example. Actual circuits should be designed based on the band

composition and the properties desired from the system.

Pin DO2 can be switched for use as pin OT-4.

Lock detection bits

The lock detection bits detect locked states in the PLL system. These systems have an unlock detection bit

(unlock bit) which is used to detect, using the reference frequency cycle, the phase difference between the

reference frequency and divided output of programmable counter. These systems also have phase error detection

bits ( bits PE1~PE3), which are capable of more precise detection (±0.55µs~±7.15µs).

1. Unlock detection bit (UNLOCK)

This bit detects, using the reference frequency cycle, the phase difference between the reference

frequency and the divided output of the programmable counter. When there is no lock, that is, when the

reference frequency and the divided output of the programmable counter are not the same, unlock F/F is set.

Unlock F/F is reset every time the input register (D2H) unlock reset bit (RESET) is set to “1”. After unlock

F/F has been reset in this way, locked state can detected by checking the unlock detection bit (UNLOCK) of

the output register (D3H). After unlock F/F has been reset, the unlock detection bit must be checked after a

time interval exceeding that of the reference frequency cycle has elapsed. This is because the reference

frequency cycle inputs the lock detection strobe to unlock F/F. If the time interval is short, the correct locked

state cannot be detected. Therefore, the output register (D3H) has a lock enable bit (ENABLE). This bit is

reset every time the input register (D2H) reset bit is set to “1”, and set to “1” through the lock detection timing.

That is, the locked state is correctly detected when the lock enable bit (ENABLE) is “1”.

HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD

REV: 1.0

18

2002.01.30.

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