LC74751 データシートの表示（PDF） - SANYO -> Panasonic

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LC74751

On-Screen Display LSI

SANYO -> Panasonic 

LC74751

Display Screen Structure (Display Example)

Specify the display of line 12 for display line ROM (64 lines).

From within line ROM, specify display control RAM for the sections where the characters are variable.

The addresses in display control RAM are automatically allocated in display order from 0 to 175 (AF hexadecimal).

Items enclosed in thick lines specify characters in display control RAM, and

items enclosed in thin lines are character specified in line ROM.

Control Data External Input Timing

Data is input in a 16-bit serial format that includes both an address and data items.

xAn address has 16 bits.

The lower 8 bits are the valid address bits. The upper 8 bits must be set to 0.

yData consists of 16 bits.

• For addresses 000 to 0AF (hexadecimal) the lower 8 bits are valid data. The upper 8 bits must be set to 0.

• For addresses 0B0 to 0BB (hexadecimal) the lower 11 bits are valid data. The upper 5 bits must be set to 0.

• For addresses 0BC to 0BF (hexadecimal) the lower 12 bits are valid data. The upper 4 bits must be set to 0.

zWhen data is input, the first 16 bits after the fall of the CS signal are acquired as the address, and then data is acquired

in 16-bit units. The address is automatically incremented ever 16 bits.

No. 5396-13/15

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