SP8855E データシートの表示（PDF） - Mitel Networks

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SP8855E

2.8GHz Parallel Load Professional Synthesiser

Mitel Networks 

SP8855E

Vcc

296

296

Vcc

40k

3k 3k

40k

296

24, 25

Fpd, Fref,

OUTPUTS

3.3mA

0V

28

27

60k

60k

50µA

50µA

0V

100µA

100µA

100µA

Fig. 7g Fpd, and Fref outputs

Fig. 7h Reference oscillator

APPLICATIONS

RF Layout

The SP8855E can operate with input frequencies up to

2.8GHz but to obtain optimum performance, good RF layout

practices should be used. A suitable layout technique is to use

double sided printed circuit board with through plated holes.

Wherever possible the top surface on which the SP8855E is

mounted should be left as a continuous sheet of copper to form

a low impedance earth plane. The ground pins 12 and 16

should be connected directly to the earth plane. Pins such as

Vcc and the unused RF input should be decoupled with chip

capacitors mounted as close to the device pin as possible with

a direct connection to the earth plane, suitable values are

10nF for the power supplies and <1nF for the RF input pin. (a

lower value should be used sufficient to give good decoupling

at the RF frequency of operation). A larger decoupling

capacitor mounted as close as possible to pin 26 should be

used to prevent modulation of VCC by the charge pump pulses.

The Rset resistor should also be mounted close to the Rset pin

to prevent noise pick-up, and the capacitor connected from the

charge pump output should be a chip component with short

connections to the SP8855E.

When the reference is derived from a crystal connected to

pins 27 and 28 as shown in Fig.5 the oscillator components are

best mounted close to the SP8855E.

All signals such as the programming inputs, RF in

reference in and the connections to the op-amp are best taken

through the pc board adjacent to the SP8855E with through

plated holes allowing connections to remote points without

fragmenting the earth plane.

Programming inputs

The input pins are designed to be compatible with TTL or

CMOS logic with a switching threshold set at about 2.4V by

three forward biased base emitter diodes. The inputs will be

taken high by an internal pull up resistor if left open circuit but

for best noise immunity it is better to connect unused inputs

directly to VCC or ground.

RF inputs

The prescaler has a differential input amplifier to improve

input sensitivity. Generally the input drive will be single ended

and the RF signal should be AC coupled to either of the inputs

using a chip capacitor. The remaining input should be

decoupled to ground , again using a chip capacitor. The inputs

can be driven differentially but the input circuit should not

provide DC path between inputs or to ground.

Lock detect circuit

The lock detect circuit uses the up and down correction

pulses from the phase detector to determine whether the loop

is in or out of lock. When the loop is locked, both up and down

pulses are very narrow compared to the reference frequency,

but the pulse width in the out of lock condition continuously

varies, depending on the phase difference between the

outputs of the reference and RF counters. The logical AND of

the up and down pulses is used to switch a 20µA current sink

to pin 18 and a 50k resistor provides a load to V . The circuit

CC

is shown in Fig.7c. When lock is established, the narrow

pulses from the phase detector ensure that the current source

is off for the majority of the time and so pin18 will be pulled high

by the 50k resistor. A voltage comparator with a switching

threshold at abount 4.7V monitors the voltage at pin 18 and

switches pin 17 low when pin 18 is more positive than the 4.7V

threshold. When the loop is unlocked, the frequency

difference at the counter outputs will produce a cyclic change

in pulse width from the phase detector outputs with a

frequency equal to the difference in frequency at the reference

and RF counter outputs. A small capacitor connected to pin 18

prevents the indication of a false phase lock conditions at pin

17 for momentaary phase coincidence. Because of the

variable width pulse nature of the signal at pin 18 the

calculation of a suitable capacitor value is complex, but if an

indication with a delay amounting to several times the

expected lock up time is acceptable, the delay will be

approximately equal to the time constant of the capacitor on

pin 18 and the internal 50k resistor.

9

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