SA9101 データシートの表示（PDF） - South African Micro Electronic Systems
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SA9101 Datasheet PDF : 40 Pages
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SA9101
S -bit access
n
Due to new signalling procedures using the five S bits (S ... S ) of every other frame
n
n0
n4
of the CRC Multiframe structure, two possibilities of access via the microprocessor are
suported:
- The standard procedure allows reading/writing the S -bit registers without further
n
support. The Sn-bit information will be updated every other frame.
- The advanced procedure, allows reading/writing two S -bit stacks each with a size
n
of 5 bytes. Two status bits (SR5B6 and SR5B7) provide an indication for updating
the stack information by reading/writing five bytes per multiframe from/to the
assigned stack address. To avoid loss of information, the status bits should be
monitored at time intervals less than 2ms (1,5ms recommended). With the first
access to a stack, the associated status bit will be reset.
A Transmit or Receive Multiframe Begin interrupt is supported when Alarm Interrupt
mode is enabled (CR5B6 and CR5B7).
If one makes use of the Sn bit stack in the Double frame format it is necessary that this
be done in conjunction with an externally enforced Multi-frame structure to ensure the
proper recovery of data on the far side. This is only possible in the Non-Transparent Mode
for Timelsot 0.
Organization of the stacks:
The sequentially received Sn bits (Sn0 up to Sn4) of odd numbered frames of the multiframe
structure are re-organized to bytes containing the Sn-information of the same level (Sn0
byte up to Sn4 byte). The Sn4 byte is the first byte to be read or written via the
microprocessor interface (refer to table 3).
Alternatively, S bits may be processed via the system interface,if one of the transparent
n
modes are enabled.
Frame
no.
Bit Slot
45678
Microprocessor
Interface
1
SSSSS
D7
n0
n1
n2
n3
n4
3
5
7
9
11
13
15
Sn0 Sn1 Sn2 Sn3 Sn4
D0
Table 3: Organisation of the Sn-Bit Stacks
sames
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