UPD705101GM-100-8ED データシートの表示（PDF） - NEC => Renesas Technology

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UPD705101GM-100-8ED

V831™ 32-BIT MICROPROCESSOR

NEC => Renesas Technology 

µPD705101

2. INTERNAL UNITS

(1) Bus control unit (BCU)

Controls the address bus, data bus, and control bus pins. The major functions of BCU are as follows:

(a) Bus arbitration

Arbitrates the bus mastership among bus masters (CPU, DRAMC, DMAC, and external bus masters). The

bus mastership can be changed after completion of the bus cycle under execution, and in an idle state.

(b) Wait control

Controls eight areas in the 16M-byte space corresponding to RAS and seven chip select signals (CS1 through

CS7). Generates chip select signals, controls wait states, and selects the type of bus cycle.

(c) DMA controller

Generates RAS and four CAS signals, and controls access to DRAM. The hyper page mode of DRAM is

supported and DRAM can be accessed in two types of cycle: normal access (off-page) and hyper page (on-

page).

(d) ROM controller

Accessing ROM with page access function is supported. The bus cycle immediately before and addresses

are compared, and wait states are controlled in the normal access (off-page) and page access (on-page)

modes. A page width of 8 bytes to 16 bytes can be supported.

(2) Interrupt controller (ICU)

Services maskable interrupt requests (INTP00 through INTP03, and INTP10 through INTP13) from internal

peripheral hardware and external sources. The priorities of these interrupt requests can be specified in units of

four groups, and edge-triggered or level-triggered interrupts can be nested.

(3) DMA controller (DMAC)

Transfers data between memory and I/O in the place of the CPU. The transfer type is 2-cycle transfer. Two transfer

modes, single transfer and demand transfer, are available.

(4) Serial interface (UART/CSI/BRG)

One asynchronous serial interface (UART) channel and one clocked serial interface (CSI) channel is provided.

As the serial clock source, the output of the baud rate generator (BRG) and the bus clock can be selected.

(5) Real-time pulse unit (RPU)

Provides timer/counter functions. The on-chip 16-bit time/event counter and 16-bit interval timer can be used

to calculate pulse intervals and frequencies, and to output programmable pulses.

(6) Clock generator (CG)

A frequency three times higher than that of an oscillator connected to the X1 and X2 pins is supplied as the

operating clock of the CPU. In addition, a bus clock (with the same cycle as the input clock) is also supplied as

the operating clock of the peripheral units. An external clock can be also input instead of connecting an oscillator.

(7) Port (PIO)

Provides port functions. Three I/O ports are available. The pins of these ports can be used as port pins or serial

control pins.

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