ICS541M データシートの表示（PDF） - Integrated Circuit Systems
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ICS541M Datasheet PDF : 4 Pages
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PRELIMINARY INFORMATION
ICS541
PLL Clock Divider
Electrical Specifications
Parameter
Conditions
Minimum Typical
ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)
Supply Voltage, VDD
Referenced to GND
Inputs
Referenced to GND
-0.5
Clock Output
Referenced to GND
-0.5
Ambient Operating Temperature
0
Soldering Temperature
Max of 10 seconds
Storage temperature
-65
DC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)
Operating Voltage, VDD
3
Input High Voltage, VIH, ICLK only, Note 1 ICLK (Pin 1)
(VDD/2)+1
Input Low Voltage, VIL, ICLK only, Note 1
ICLK (Pin 1)
Input High Voltage, VIH
S0, S1, OE
2
Input Low Voltage, VIL
S0, S1, OE
Output High Voltage, VOH
IOH=-25mA
2.4
Output Low Voltage, VOL
IOL=25mA
Output High Voltage, VOH, CMOS level
IOH=-4mA
VDD-0.4
IDD Operating Supply Current, 80 in, 40+20 out No Load, 5.0V
15
IDD Operating Supply Current, 40 in, 40+20 out No Load, 3.3V
8
Short Circuit Current
Each Output
±70
Input Capacitance, S1, S0, OE
Pins 4, 5, 6
4
AC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)
Input Frequency, clock input
at VDD = 5V
4
Input Frequency, clock input
at VDD = 3.3V
4
Skew of output clocks
rising edges at VDD/2
Output Clock Rise Time
0.8 to 2.0V
1
Output Clock Fall Time
2.0 to 0.8V
1
Output Clock Duty Cycle
at VDD/2
45
49 to 51
Maximum
7
VDD+0.5
VDD+0.5
70
260
150
5.5
(VDD/2)-1
0.8
0.4
156
135
500
55
Note 1: CMOS level input; nominal trip point is VDD/2.
Units
V
V
V
C
C
C
V
V
V
V
V
V
V
V
mA
mA
mA
pF
MHz
MHz
ps
ns
ns
%
MDS 541 B
3
Revision 082500
Printed 11/14/00
Integrated Circuit Systems, Inc. •525 Race Street• San Jose•CA• 95126• (408)295-9800tel • www.icst.com
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