8254 データシートの表示（PDF） - Intel
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8254 Datasheet PDF : 21 Pages
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8254
A C CHARACTERISTICS TA e 0 C to 70 C VCC e 5V g10% GND e 0V (Continued)
WRITE CYCLE
Symbol
Parameter
8254
8254-2
Unit
Min
Max
Min
Max
tAW
v Address Stable Before WR
0
0
ns
tSW
v CS Stable Before WR
0
0
ns
tWA
v Address Hold Time After WR
0
0
ns
tWW
WR Pulse Width
150
95
ns
tDW
u Data Setup Time Before WR
120
95
ns
tWD
u Data Hold Time After WR
0
0
ns
tRV
Command Recovery Time
200
165
ns
CLOCK AND GATE
Symbol
Parameter
8254
8254-2
Unit
Min
Max
Min
Max
tCLK
tPWH
tPWL
tR
tF
tGW
tGL
tGS
tGH
tOD
tODG
tWC
tWG
tWO
tCL
Clock Period
125
DC
100
DC
ns
High Pulse Width
60(3)
30(3)
ns
Low Pulse Width
60(3)
50(3)
ns
Clock Rise Time
25
25
ns
Clock Fall Time
25
25
ns
Gate Width High
50
50
ns
Gate Width Low
50
50
ns
u Gate Setup Time to CLK
50
40
ns
u Gate Setup Time After CLK
50(2)
50(2)
ns
v Output Delay from CLK
150
100
ns
v Output Delay from Gate
120
100
ns
v CLK Delay for Loading
0
55
0
55
ns
Gate Delay for Sampling
b5
50
b5
40
ns
OUT Delay from Mode Write
260
240
ns
CLK Set Up for Count Latch
b40
45
b40
40
ns
NOTES
2 In Modes 1 and 5 triggers are sampled on each rising clock edge A second trigger within 120 ns (70 ns for the 8254-2) of
the rising clock edge may not be detected
3 Low-going glitches that violate tPWH tPWL may cause errors requiring counter reprogramming
4 Sampled not 100% tested TA e 25 C
5 If CLK present at TWC min then Count equals Na2 CLK pulses TWC max equals Count Na1 CLK pulse TWC min to
TWC max count will be either Na1 or Na2 CLK pulses
6 In Modes 1 and 5 if GATE is present when writing a new Count value at TWG min Counter will not be triggered at TWG
max Counter will be triggered
7 If CLK present when writing a Counter Latch or ReadBack Command at TCL min CLK will be reflected in count value
latched at TCL max CLK will not be reflected in the count value latched
19
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