TLIU04C1 データシートの表示（PDF） - Agere -> LSI Corporation

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TLIU04C1

Quad T1/E1 Line Interface

Agere -> LSI Corporation 

Advance Data Sheet, Rev. 2

April 1999

TLIU04C1 Quad T1/E1 Line Interface

Microprocessor Mode (continued)

Receiver Configuration Modes (continued)

Alternate Logic Mode (ALM)

The alternate logic mode (ALM) control bit (register 5,

bit 5) selects the receive and transmit data polarity (i.e.,

active-high vs. active-low). If ALM = 0, the receiver cir-

cuitry (and transmit input) assumes the data to be

active-low polarity. If ALM = 1, the receiver circuitry

(and transmit input) assumes the data to be active-high

polarity. The ALM control is used in conjunction with

the ACM control (register 5, bit 6) to determine the

receive data retiming mode.

Alternate Clock Mode (ACM)

The alternate clock mode (ACM) control bit (register 5,

bit 6) selects the positive or negative clock edge of the

receive clock (RCLK) for receive data retiming. The

ACM control is used in conjunction with ALM

(register 5, bit 5) control to determine the receive data

retiming modes. If ACM = 1, the receive data is retimed

on the positive edge of the receive clock. If ACM = 0,

the receive data is retimed on the negative edge of the

receive clock. Note that this control does not affect the

timing relationship for the transmitter inputs. See

Figure 23 on page 59.

RLIU Alarms

Analog Loss of Signal (ALOS) Alarm. An analog sig-

nal detector monitors the receive signal amplitude and

reports its status in the analog loss of signal alarm bits

in registers 0 and 1. Analog loss of signal is indicated

(ALOS = 1) if the amplitude at the RRING and RTIP

inputs drops more than approximately 18 dB below the

nominal signal amplitude. The ALOS alarm condition

will clear when the receive signal amplitude returns to

greater than 14 dB below normal. In this way, the ALOS

circuitry provides 4 dB of hysteresis to prevent alarm

chattering. The ALOS alarm status bit will latch the

alarm and remain set until being cleared by a read

(clear on read). Upon the transition from ALOS = 0 to

ALOS = 1, a microprocessor interrupt will be generated

if the corresponding ALOS interrupt mask bit (MALOS;

registers 2 and 3, bits 0 and 4), the channel mask bit

(MASK; registers 6—9, bit 1), or the global mask bit

(GMASK; register 4, bit 0) is not set.

The time required to detect ALOS is selectable. When

ALTIMER = 0 (register 12, bit 0), ALOS is declared

between 1 ms and 2.6 ms after losing signal as

required by I.431(3/93) and ETS-300-233 (5/94). If

ALTIMER = 1, ALOS is declared between 10 and 255

bit symbol periods after losing signal as required by

G.775 (11/95). The timing is derived from the XCLK

clock. The detection time is independent of signal

amplitude before the loss condition occurs. Normally,

ALTIMER = 1 would be used only in CEPT mode since

no T1/DS1 standards require this mode. In T1/DS1

mode, this bit should normally be zero.

The behavior of the receiver LIU outputs under ALOS

conditions is dependent on the loss shutdown control

bit (LOSSD; register 5, bit 7) in conjunction with the

receive alarm indication select control bit (RCVAIS;

register 12, bit 1) as described in the Loss Shutdown

(LOSSD) and Receiver AIS (RCVAIS) section on

page 22.

Digital Loss of Signal (DLOS) Alarm. A digital loss of

signal (DLOS) detector guarantees the received signal

quality as defined in the appropriate ANSI, Bellcore,

and ITU standards. The digital loss of signal alarms are

reported in the alarm status registers 0 and 1. During

DS1 operation, digital loss of signal (DLOS = 1) is indi-

cated if 100 or more consecutive zeros occur in the

receive data stream. The DLOS condition is deacti-

vated when the average ones density of at least 12.5%

is received in 100 contiguous pulse positions. The

DLOS alarm status bit will latch the alarm and remain

set until being cleared by a read (clear on read). The

LOSSTD control bit (register 4, bit 2) selects the con-

formance protocols for the DLOS alarm indication per

Table 8. Setting LOSSTD = 1 adds an additional con-

straint that there are less than 15 consecutive zeros in

the DS1 data stream before DLOS is deactivated.

Lucent Technologies Inc.

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