CD4502BMS データシートの表示（PDF） - Intersil
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CD4502BMS Datasheet PDF : 8 Pages
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Specifications CD4502BMS
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
Static Burn-In 1 2, 5, 7, 9, 11, 14 1, 3, 4, 6, 8, 10, 12,
16
Note 1
13, 15
Static Burn-In 2 2, 5, 7, 9, 11, 14
8
1, 3, 4, 6, 10, 12,
Note 1
13, 15, 16
Dynamic Burn-
-
In Note 1
8
16
2, 5, 7, 9, 11, 14
4
1, 3, 6, 10, 12, 13,
15
Irradiation
2, 5, 7, 9, 11, 14
8
1, 3, 4, 6, 10, 12,
Note 2
13, 15, 16
NOTES:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
Logic Diagram
DI *
3-STATE
OUTPUT
*
DISABLE
INHIBIT *
INVERTER/BUFFER NO. 1
VDD
Q1
TO 5 OTHER
INVERTER/BUFFERS
VSS
VDD
* ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
VSS
TRUTH TABLE
DISABLE INHIBIT
Dn
Qn
0
0
0
1
0
0
1
0
0
1
X
0
1
X
X
Z
Logic 0 = Low
Logic 1 = High
Z = High Impedance
X = Don’t Care
FIGURE 1. LOGIC DIAGRAM OF 1 OF 6 IDENTICAL INVERTER/BUFFERS
Test Circuit and Waveform
PULSE
GENERATOR
D3 1
Q3 2
D1 3
DISABLE 4
Q1 5
D2 6
Q2 7
VSS 8
16 VDD
15 D6
14 Q6
13 D5
12 INHIBIT
11 Q5
10 D4
9 Q4
TEST CONDITIONS
TEST PIN 15 POINT A
tPHZ VSS
VSS
tPLZ VDD
VDD
tPZL VDD
VDD
tPZH VSS
VSS
VDD
0.01kµF
1kΩ
A
CL
50%
tPLZ
tPHZ
10%
90%
50%
tPZL
90%
10%
tPZH
VDD
VOL
VOH
VSS
FIGURE 2. DISABLE DELAY TIMES TEST CIRCUIT AND WAVEFORMS
7-478
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