MCM63Z737TQ15 データシートの表示（PDF） - Motorola => Freescale
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MCM63Z737TQ15
Motorola => Freescale
MCM63Z737TQ15 Datasheet PDF : 20 Pages
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AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V ± 5%, TA = 0 to 70°C Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20% to 80%)
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . See Figure 6 Unless Otherwise Noted
RθJA Under Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBD
READ/WRITE CYCLE TIMING (See Notes 1 and 2)
MCM63Z737–11
MCM63Z819–11
66 MHz
MCM63Z737–15
MCM63Z819–15
50 MHz
Parameter
Symbol
Min
Max
Min
Max
Unit Notes
Cycle Time
Clock High Pulse Width
tKHKH
15
—
20
—
ns
tKHKL
6
—
8
—
ns
3
Clock Low Pulse Width
Clock Access Time
tKLKH
6
—
8
—
ns
3
tKHQV
—
11
—
15
ns
Output Enable to Output Valid
Clock High to Output Active
Output Hold Time
tGLQV
—
6
—
7
ns
tKHQX1
1.5
—
1.5
—
ns
4, 5
tKHQX
1.5
—
1.5
—
ns
4
Output Enable to Output Active
Output Disable to Q High–Z
Clock High to Q High–Z
tGLQX
0
—
0
—
ns
4, 5
tGHQZ
—
4.5
—
5
ns
4, 5
tKHQZ
1.5
4.5
1.5
5
ns
4, 5
Setup Times:
Address tADKH
2.5
—
2.5
—
ns
ADV tLVKH
2.5
2.5
Data In tDVKH
2
2
Write tWVKH
2.5
2.5
Chip Enable tEVKH
2.5
2.5
Clock Enable tCVKH
2.5
2.5
Hold Times:
Address tKHAX
0.5
—
0.5
—
ns
ADV tKHLX
0.5
0.5
Data In tKHDX
0.5
0.5
Write tKHWX
0.5
0.5
Chip Enable tKHEX
0.5
0.5
Clock Enable tKHCX
0.5
0.5
NOTES:
1. Write is defined as any SBx and SW low. Chip enable is defined as SE1 low, SE2 high, and SE3 low whenever ADV is low.
2. All read and write cycle timings are referenced from CK or G.
3. In order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between
data sheet parameters and actual system performance, FSRAM AC parametric specifications are always specified at VDDQ/2. In some
design exercises, it is desirable to evaluate timing using other reference levels. Since the maximum test input edge rate is known and is
given in the AC Test Conditions section of the data sheet as 1 V/ns, one can easily interpolate timing values to other reference levels.
4. This parameter is sampled and not 100% tested.
5. Measured at ± 200 mV from steady state.
OUTPUT
Z0 = 50 Ω
RL = 50 Ω
1.5 V
Figure 6. AC Test Load
MCM63Z737DMCM63Z819
12
MOTOROLA FAST SRAM
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