MCM63Z818TQ133 データシートの表示（PDF） - Motorola => Freescale
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MCM63Z818TQ133
Motorola => Freescale
MCM63Z818TQ133 Datasheet PDF : 20 Pages
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AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V ± 5%, TA = 0 to 70°C Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20% to 80%)
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . See Figure 6 Unless Otherwise Noted
RθJA Under Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBD
READ/WRITE CYCLE TIMING (See Notes 1 and 2)
MCM63Z736–133
MCM63Z818–133
133 MHz
MCM63Z736–100
MCM63Z818–100
100 MHz
Parameter
Symbol
Min
Max
Min
Max
Unit Notes
Cycle Time
Clock High Pulse Width
tKHKH
7.5
—
10
—
ns
tKHKL
3
—
4
—
ns
3
Clock Low Pulse Width
Clock Access Time
tKLKH
3
—
4
tKHQV
—
4.2
—
—
ns
3
5
ns
Output Enable to Output Valid
Clock High to Output Active
Output Hold Time
tGLQV
—
4.2
—
5
ns
tKHQX1
1.5
—
1.5
—
ns
4, 5
tKHQX
1.5
—
1.5
—
ns
4
Output Enable to Output Active
Output Disable to Q High–Z
Clock High to Q High–Z
tGLQX
0
—
0
—
ns
4, 5
tGHQZ
—
3.5
—
3.5
ns
4, 5
tKHQZ
1.5
3.5
1.5
3.5
ns
4, 5
Setup Times:
Address tADKH
2
—
2.2
—
ns
ADV
tLVKH
2
2.2
Data In tDVKH
1.7
2
Write tWVKH
2
2.2
Chip Enable tEVKH
2
2.2
Clock Enable tCVKH
2
2.2
Hold Times:
Address tKHAX
0.5
—
0.5
—
ns
ADV
tKHLX
Data In tKHDX
Write tKHWX
Chip Enable tKHEX
Clock Enable tKHCX
NOTES:
1. Write is defined as any SBx and SW low. Chip Enable is defined as SE1 low, SE2 high, and SB3 low whenever ADV is low.
2. All read and write cycle timings are referenced from CK or G.
3. In order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between
data sheet parameters and actual system performance, FSRAM AC parametric specifications are always specified at VDDQ/2. In some de-
sign exercises, it is desirable to evaluate timing using other reference levels. Since the maximum test input edge rate is known and is given
in the AC test conditions section of the data sheet as 1 V/ns, one can easily interpolate timing values to other reference levels.
4. This parameter is sampled and not 100% tested.
5. Measured at ± 200 mV from steady state.
OUTPUT
Z0 = 50 Ω
RL = 50 Ω
1.5 V
Figure 6. AC Test Load
MCM63Z736DMCM63Z818
12
MOTOROLA FAST SRAM
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