K
ADSC
STOP CLOCK WITH DESELECT OPERATION TIMING
SE1
DATA IN
VIH OR VIL FIXED (SEE NOTE)
DQx
DATA
DATA
HIGH–Z
CONTINUE
BURST READ
CLOCK STOP
(DESELECTED)
WAKE UP
(DESELECTED)
NOTE: While the clock is stopped, DATA IN must be fixed in a high (VIH) or low (VIL) state to reduce the DC current of
the input buffers. For lowest power operation, all data and address lines should be held in a low (VIL) state and
control lines held in an inactive state.
MCM69F735
14
MOTOROLA FAST SRAM