RM5231-200-QI データシートの表示（PDF） - PMC-Sierra

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RM5231-200-QI

Microprocessor with 32-Bit System Bus

PMC-Sierra 

RM5231™ Microprocessor with 32-bit System Bus Data Sheet

Released

Floating-point operations includes:

• add

• subtract

• multiply

• divide

• square root

• reciprocal

• reciprocal square root

• conditional moves

• conversion between fixed-point and floating-point format

• conversion between floating-point formats, and floating-point compare.

Table 2 gives the latencies of the floating-point instructions in internal processor cycles.

Table 2 Floating-Point Instruction Cycles

Operation

Latency

Repeat Rate

fadd

4

1

fsub

4

1

fmult

4/5

1/2

fmadd

4/5

1/2

fmsub

4/5

1/2

fdiv

21/36

19/34

fsqrt

21/36

19/34

frecip

21/36

19/34

frsqrt

38/68

36/66

fcvt.s.d

4

1

fcvt.s.w

6

3

fcvt.s.l

6

3

fcvt.d.s

4

1

fcvt.d.w

4

1

fcvt.d.l

4

1

fcvt.w.s

4

1

fcvt.w.d

4

1

fcvt.l.s

4

1

fcvt.l.d

4

1

fcmp

1

1

fmov

1

1

fmovc

1

1

fabs

1

1

fneg

1

1

Note: Numbers are represented as single/double precision format.

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

14

Document ID: PMC-2002165, Issue 1

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