DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

UPD488448FB-C80-45-DQ1 データシートの表示(PDF) - NEC => Renesas Technology

部品番号
コンポーネント説明
メーカー
UPD488448FB-C80-45-DQ1
NEC
NEC => Renesas Technology NEC
UPD488448FB-C80-45-DQ1 Datasheet PDF : 80 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
µPD488448 for Rev. P
Table 3-3 shows the COP field encoding. The device must be in the ATTN power state in order to receive COLC
packets. The COLC packet is used primarily to specify RD (read) and WR (write) commands. Retire operations
(moving data from the write buffer to a sense amp) happen automatically. See Figure 15-1 for a more detailed
description.
The COLC packet can also specify a PREC command, which precharges a bank and its associated sense amps.
The RDA/WRA commands are equivalent to a combining RD/WR with a PREC. RLXC (relax) performs a power mode
transition. See 23. Power State Management.
Table 3-3 COLC Packet Field Encodings
S DC4..DC0
(select device) Note1
COP3..0 Name
Command Description
0 ----
1 /= (DEVID4..0)
1 == (DEVID4..0)
1 == (DEVID4..0)
1 == (DEVID4..0)
1 == (DEVID4..0)
1 == (DEVID4..0)
1 == (DEVID4..0)
1 == (DEVID4..0)
1 == (DEVID4..0)
1 == (DEVID4..0)
-----
-----
x000 Note2
x001
NOCOP
WR
x010
x011
x100
RSRV
RD
PREC
x101
WRA
x110
x111
1xxx
RSRV
RDA
RLXC
No operation.
Retire write buffer of this device.
Retire write buffer of this device.
Retire write buffer of this device, then write column C5..C0 of bank
BC4..BC0 to write buffer.
Reserved, no operation.
Read column C5..C0 of bank BC4..BC0 of this device.
Retire write buffer of this device, then precharge bank BC4..BC0 (see
Figure 12-2).
Same as WR, but precharge bank BC4..BC0 after write buffer (with new
data) is retired.
Reserved, no operation.
Same as RD, but precharge bank BC4..BC0 afterward.
Move this device into the standby (STBY) power state (see Figure 23-2).
Notes 1. “/=” means not equal, “==” means equal.
2. An “x” entry indicates which commands may be combined. For instance, the two commands WR/RLXC
may be specified in one COP value(1001).
Table 3-4 shows the COLM and COLX field encodings. The M bit is asserted to specify a COLM packet with two 8
bit bytemask fields MA and MB. If the M bit is not asserted, an COLX is specified. It has device and bank address
fields, and an opcode field. The primary use of the COLX packet is to permit an independent PREX (precharge)
command to be specified without consuming control bandwidth on the ROW pins. It is also used for the CAL
(calibrate) and SAM (sample) current control commands (see 25. Current and Temperature Control), and for the
RLXX power mode command (see 23. Power State Management).
Table 3-4 COLM Packet and COLX Packet Field Encodings
M DX4..DX0
XOP4..0 Name
(select device)
Command Description
1 ----
-
MSK
MB/MA bytemasks used by WR/WRA.
0 /= (DEVID4..0) -
No operation.
0 == (DEVID4..0) 00000 NOXOP No operation.
0 == (DEVID4..0) 1xxx0 Note PREX
Precharge bank BX4..BX0 of this device (see Figure 12-2).
0 == (DEVID4..0) x10x0 CAL
Calibrate (drive) IOL current for this device (see Figure 25-1).
0 == (DEVID4..0) x11x0 CAL / SAM Calibrate (drive) and Sample (update) IOL current for this device (see Figure 25-1).
0 == (DEVID4..0) xxx10 RLXX
Move this device into the standby (STBY) power state (see Figure 23-2).
0 == (DEVID4..0) xxxx1 RSRV
Reserved, no operation.
Note An “x” entry indicates which commands may be combined. For instance, the two commands PREX/RLXX
may be specified in one XOP value (10010).
14
Data Sheet M14837EJ3V0DS00

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]