CDP68HC68S1 データシートの表示（PDF） - Intersil
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CDP68HC68S1 Datasheet PDF : 14 Pages
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CDP68HC68S1
SPI Mode, Software
The SPl mode is similar to SCl mode in that the user micro-
computer sends/receives data to/from the SBl chip 1 byte at
a time. In the SPI mode, however, the user microcomputer
must reverse the bit order of transmitted and received bytes.
When transmitting a message, each bit of a transmitted byte
is simultaneously transmitted onto the bus and a reflected bit
is simultaneously received from the bus.
Monitor and Control of the CONTROL Line
In the SPl mode, the user microcomputer monitors the CON-
TROL pin on the SBl chip in order to determine if the SBlC is
ready to accept a transmit request. Actually, a data collision
may still occur and the user microcomputer must always be
ready to handle it.
The CONTROL signal is normally high and goes low when
data is on the bus or when pulled low by the user microcom-
puter. After being pulled low by the user microcomputer, which
signals a request to begin the transmission data, the CON-
TROL signal will latch low and stay low until the middle of the
last data bit has been transmitted and appears on the bus.
The CONTROL signal will also go low at the beginning of the
first data bit, when received from the bus. It will then go high
at the middle of the last data bit.
When the SBl chip begins to receive a byte of data from the
bus and the user microcomputer has not pulled the SBlC’s
CONTROL line low, the SBl chip will pull CONTROL low and
start generating the SCK clock signal. As each data bit is
received it is clocked out of the SBl chip and into the user
microcomputer. Any data in the user microcomputer’s SPl
data register will be transferred out and into the SBl chip.
The CONTROL signal will go high at the midpoint of the
eighth data bit. This will allow the user microcomputer to
have enough time to review the just received SPl data and
reload it, if further data is needed to be transmitted. How-
ever, it must again pull the CONTROL pin low to signal he
SBl chip that it should begin transmitting. As a slave to he
SBl chip, the user microcomputer must be able to and le the
incoming data on the SPl port without affecting its other soft-
ware routine functions.
Detecting IDLE via a User Microcomputer External
Interrupt
The user microprocessor’s external interrupt should be set
to edge detect IDLE for falling transitions, i.e. EOM detec-
tion. If possible, detect CONTROL for rising transitions, for
byte transmission/reception complete detection.
Use of Internal User Microcomputer Flags and Interrupts
The normally available SPl finished flag (SPlF) and optionally
its associated interrupt may be used by the user microcomputer
to know when a byte transmission/reception of is complete.
The user microcomputer should be ready to handle the Write
Collision, WCOL, error flag. The WCOL flag is set when a
collision is detected in the SPl port. This will occur when the
user microcomputer tries to load a byte into the SPI data
register after the SBl chip has already begun to load data
into the SPl port.
Sending Messages to Other Microcomputers on the Bus
ln order to send a message to other microcomputers on the
bus while in the SPI mode the user microcomputer should:
1. Monitor the IDLE pin and determine if the bus is currently
busy or if a transmission may be immediately started.
2. Monitor CONTROL to determine if it is ok to load the byte
to be transmitted into the user microcomputer’s SPl data
register.
3. Load the byte to be transmitted into the SPl data register.
4. Pull the CONTROL pin low to signal the SBl chip to start
a byte transmit cycle.
5. Wait until the byte transmit cycle is completed as signaled
by the SPl Finished, SPlF, flag/interrupt in the SPl port or
by the CONTROL signal going high.
6. Compare the received byte with the last transmitted byte.
7. If the received byte equals the last transmitted byte, and
more bytes remain to be transmitted, then continue the
cycle with step #3. If there are more messages to trans-
mit, then go to step #1. If there are no more bytes to be
transmitted, then consider the message as having been
transmitted, and generate an End Of Message (EOM)
(i.e. delay for 10 contiguous bit times). Go to step #1.
8. If the received byte does not equal the last transmitted
byte and this is the first byte of a message, then treat the
received byte as the first byte of a received message (i.e.
the ID byte). Attempt to retransmit the previous message
after the IDLE signal has gone low again. If this happens
during the transmission of a later message byte, other
than the ID byte, then consider it due to either an errone-
ous data collision on the bus or due to noise collisions on
the bus causing the message to have to be re-transmit-
ted. Go to step #1.
Framing Errors
While in the SPl mode, the SBl chip is capable of detecting
incoming framing errors. If one is detected, generation of the
SCK pulses to the user microcomputer is terminated. The
SBl chip essentially quits receiving data and starts looking
for an End Of Message. Resetting of the SCK generator will
occur upon receiving an EOM. Meanwhile, software must be
prepared to resynchronize the micro’s SPl port; this can be
done by disabling and then reinitializing it.
Even though the SBl chip can detect framing errors, it can
not flag the user microcomputer that one has occurred.
Since the previously received byte has already been trans-
ferred to the user microcomputer, the SBI chip will simply
refuse to accept any further incoming data until an EOM
occurs. Thus, one way that the user microcomputer may
detect that the received data is valid, is via using a check
sum byte imbedded within each message. Another way
would be to compare the number of bytes received fora par-
ticular ID to the number expected for that ID.
Buffered SPI Mode, Hardware
The MOSl and MlSO pins on the user microcomputer should
be connected to the XMlT and REC pins of the SBl chip
respectively. The SCK pins on the user microcomputer and
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