V54C3128404VALS6 データシートの表示（PDF） - Mosel Vitelic Corporation

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V54C3128404VALS6

128Mbit SDRAM 3.3 VOLT, TSOP II / SOC PACKAGE 8M X 16, 16M X 8, 32M X 4

Mosel Vitelic Corporation  

MOSEL VITELIC

Timing Diagrams (Cont’d)

15. Random Column Read ( Page within same Bank)

15.1 CAS Latency = 2

15.2 CAS Latency = 3

16. Random Column Write ( Page within same Bank)

16.1 CAS Latency = 2

16.2 CAS Latency = 3

17. Random Row Read ( Interleaving Banks) with Precharge

17.1 CAS Latency = 2

17.2 CAS Latency = 3

18. Random Row Write ( Interleaving Banks) with Precharge

18.1 CAS Latency = 2

18.2 CAS Latency = 3

19. Precharge Termination of a Burst

19.1 CAS Latency = 2

19.2 CAS Latency = 3

V54C3128(16/80/40)4V(T/S)

V54C3128(16/80/40)4V(T/S) Rev. 1.5 March 2003

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