MU9C8K64-50TDC データシートの表示（PDF） - Music Semiconductors
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MU9C8K64-50TDC Datasheet PDF : 30 Pages
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Pin Descriptions
MU9C Binary Routing Coprocessor (RCP) Family
PIN DESCRIPTIONS
Note: Signal names that start with a slash (“/”) are active LOW.
All signals are 3.3V CMOS level. Never leave inputs floating.
The CAM architecture draws large currents during compare
operations, mandating the use of good layout and bypassing
techniques. Refer to the Electrical Characteristics section for
more information.
DQ31–0 (Data Bus, Three-state, Common Input/
Output)
The DQ31–0 lines convey data to and from the MU9C
RCP. When the /E input is HIGH the DQ31–0 lines are
held in their high-impedance state. The /W input
determines whether data flows to or from the device on the
DQ31–0 lines. The source or destination of the data is
determined by the AC bus, DSC, and the /AV line. During
a Write cycle, data on the DQ31–0 lines is registered by
the falling edge of /E.
AC12–0/AC11–0 (Address/Control Bus, Input)
When Hardware control is selected, the AC bus conveys
address or control information to the MU9C RCP,
depending on the state of the /AV input. When /AV is
LOW then the AC bus carries an address; when /AV is
HIGH the AC bus carries control information. Data on the
AC bus is registered by the falling edge of /E. When
software control is selected, the state of the AC bus does
not affect the operation of the device.
DSC (Data Segment Control, Input)
When DQ bus access to a 64 bit register or memory word
is performed, the DSC input determines whether bits 31–0
(DSC LOW) or bits 63–32 (DSC HIGH) are accessed.
Access to 32 bit registers require that DSC be held LOW.
AA12–0/AA11–0 (Active Address, Output)
The AA bus conveys the Match address, the Next Free
address, or Random Access address, depending on the
most recent memory cycle. The /OE input enables the AA
bus; when the /OE input is HIGH, the AA bus is in its
high-impedance state; when /OE is LOW the AA bus is
active. In a vertically cascaded system after a Comparison
cycle, Write at Next Free Address cycle or Read/Write at
Highest-Priority match, only the highest-priority device
will enable its AA bus, regardless of the state of the /OE
input. In the event of a mismatch in the Address Database
after a Compare cycle, or after a Write at Next Free
Address cycle into an already full system, the
lowest-priority device will drive the AA bus with all 1s.
The AA bus is latched when /E is LOW, and are free to
change only when /E is HIGH.
Rev. 6
DQ0
81
DQ1
82
DQ2
83
DQ3
84
VDD
85
DQ4
86
DQ5
87
DQ6
88
DQ7
89
VSS
90
DQ8
91
DQ9
92
DQ10
93
DQ11
94
VDD
95
DQ12
96
DQ13
97
DQ14
98
DQ15
99
VSS
10 0
MU9CxK64
100-Pin LQFP
(Top View)
Figure 3: MU9C RCP Pinout
50
AA12/NC*
49
AC11
48
AC10
47
AC9
46
AC8
45
VSS
44
AC7
43
AC6
42
AC5
41
AC4
40
VDD
39
AC3
38
AC2
37
AC1
36
AC0
35
VSS
34
TDO
33
TDI
32
TMS
31
TCLK
* NC on MU9C4K64
3
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