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M5-192/256-7YI/1 データシートの表示(PDF) - Lattice Semiconductor
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M5-192/256-7YI/1
Fifth Generation MACH Architecture
Lattice Semiconductor
M5-192/256-7YI/1 Datasheet PDF : 47 Pages
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BLOCK DIAGRAM — M5(LV)-128/XXX
Block A/Macrocells 0-15
SEGMENT 0
Block D/Macrocells 0-15
I0,
1
2
16
16
I/O Cells
2
32
2 PT OE
16
Macrocells
Control
Generator
7
64 PT
7 PT
64 x 73
AND Logic Array
and Logic Allocator
16
16
I/O Cells
2
32
2 PT OE
16
Macrocells
Control
Generator
7
64 PT
7 PT
64 x 73
AND Logic Array
and Logic Allocator
32
32
Block Interconnect
32
32
32
2
16
64 x 73
AND Logic Array
and Logic Allocator
64 PT
7 PT
Macrocells
16
I/O Cells
Control
7
Generator
2 PT OE
16
32
2
16
64 x 73
AND Logic Array
and Logic Allocator
64 PT
7 PT
Macrocells
16
I/O Cells
Control
7
Generator
2 PT OE
16
Block B/Macrocells 0-15
Block C/Macrocells 0-15
CLK0
CLK1
CLK2
4
CLK3
SEG M E NT I NT E R C O N N E CT
Block A/Macrocells 0-15
Block D/Macrocells 0-15
I2,
3
2
16
16
I/O Cells
2
32
2 PT OE
16
Macrocells
Control
Generator
7
64 PT
7 PT
64 x 73
AND Logic Array
and Logic Allocator
16
16
I/O Cells
2
32
2 PT OE
16
Macrocells
Control
Generator
7
64 PT
7 PT
64 x 73
AND Logic Array
and Logic Allocator
32
32
Block Interconnect
32
32
32
2
64 x 73
AND Logic Array
and Logic Allocator
64 PT
7 PT
Macrocells
16
Control
7
Generator
2 PT OE
I/O Cells
16
16
32
2
16
64 x 73
AND Logic Array
and Logic Allocator
64 PT
7 PT
Macrocells
16
Control
7
Generator
2 PT OE
I/O Cells
16
Block B/Macrocells 0-15
Block C/Macrocells 0-15
SEGMENT 1
20446G-007
14
MACH 5 Family
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