M5-192/104-15HI/1 データシートの表示（PDF） - Lattice Semiconductor
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M5-192/104-15HI/1 Datasheet PDF : 47 Pages
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M5(LV) TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED)
-5
-6
-7
-10
-12
-15
-20
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit
Power Delays:
tPL1 Power level 1 delay (Note 2)
4.0
(5.0)
4.0
4.0
(5.0)
4.0
(5.0)
4.0
(5.0)
4.0
(5.0)
4.0
(5.0)
ns
tPL2 Power level 2 delay (Note 2)
6.0
(9.0)
6.0
6.0
(9.0)
6.0
(9.0)
6.0
(9.0)
6.0
(9.0)
6.0
(9.0)
ns
tPL3 Power level 3 delay (Note 2)
9.0
9.0
9.0
9.0
9.0
9.0
9.0 ns
(17.5)
(17.5)
(17.5)
(17.5)
(17.5)
(17.5)
Additional Cluster Delay:
tPT Product term cluster delay
Interconnect Delays:
0.3
0.3
0.3
0.3
0.3
0.3
0.3 ns
tBLK Block interconnect delay
tSEG Segment interconnect delay
Reset and Preset Delays:
1.5
1.5
1.5
2.0
2.0
2.0
2.0 ns
4.5
4.5
5.0
6.0
6.0
6.0
6.0 ns
tSRi
Asynchronous reset or preset to internal
register output
6.0
8.0
8.0
10.0
12.0
14.0
16.0 ns
tSR
Asynchronous reset or preset to register
output
8.0
10.0
10.0
12.0
14.0
16.0
18.0 ns
tSRR Reset and set register recovery time
5.5
7.5
7.5
8.0
9.0
10.0
11.0
ns
tSRW Asynchronous reset or preset width
3.0
4.0
4.0
5.0
6.0
7.0
8.0
ns
Clock Enable Delays:
tCES Clock enable setup time
tCEH Clock enable hold time
Width:
4.0
5.0
5.0
6.0
7.0
7.0
8.0
ns
3.0
4.0
4.0
5.0
6.0
6.0
7.0
ns
tWLS Global clock width low (Note 3)
2.5
3.0
3.0
4.0
5.0
6.0
6.0
ns
tWHS Global clock width high (Note 3)
2.5
3.0
3.0
4.0
5.0
6.0
6.0
ns
tWLA Product term clock width low
3.0
4.0
4.0
5.0
6.0
7.0
8.0
ns
tWHA Product term clock width high
3.0
4.0
4.0
5.0
6.0
7.0
8.0
ns
tGWA
Gate width low (for low transparent) or
high (for high transparent)
3.0
4.0
4.0
5.0
6.0
7.0
8.0
ns
tWIR Input register clock width low or high 3.0
4.0
4.0
5.0
6.0
7.0
8.0
ns
24
MACH 5 Family
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