M5-256/104-10VC/1 データシートの表示（PDF） - Lattice Semiconductor

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M5-256/104-10VC/1

Fifth Generation MACH Architecture

Lattice Semiconductor 

352-BALL BGA CONNECTION DIAGRAM — M5-512, M5LV-512

Bottom View (I/O Pin-outs)

352-Ball BGA

Pin Designations

CLK = Clock

GND = Ground

I

= Input

I/O = Input/Output

NC = No Connect

VCC = Supply Voltage

TDI = Test Data In

TCK = Test Clock

TMS = Test Mode Select

TDO = Test Data Out

7 D 15

MACH 5 Family

Macrocell (0-15)

PAL Block (A-D)

Segment (0-7)

20446G-031

43

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