PIC18F010T-I/SN データシートの表示（PDF） - Microchip Technology

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PIC18F010T-I/SN

High Performance Microcontrollers

Microchip Technology 

PIC18F010/020

3.0 RESET

The PIC18F010/020 differentiates between various

kinds of RESET:

a) Power-on Reset (POR)

b) MCLR Reset during normal operation

c) MCLR Reset during SLEEP

d) Watchdog Timer (WDT) Reset (during normal

operation)

e) Programmable Brown-out Reset (BOR)

f) RESET Instruction

g) Stack Full Reset

h) Stack Underflow Reset

Most registers are unaffected by a RESET. Their status

is unknown on POR and unchanged by all other

RESETS. The other registers are forced to a “RESET

state” on Power-on Reset, MCLR, WDT Reset, Brown-

out Reset, MCLR Reset during SLEEP and by the

RESET instruction.

Most registers are not affected by a WDT wake-up,

since this is viewed as the resumption of normal oper-

ation. Status bits from the RCON register, RI, TO, PD,

POR and BOR, are set or cleared differently in different

RESET situations, as indicated in Table 3-2. These bits

are used in software to determine the nature of the

RESET. See Table 3-3 for a full description of the

RESET states of all registers.

A simplified block diagram of the on-chip RESET circuit

is shown in Figure 3-1.

The Enhanced MCU devices have a MCLR noise filter

in the MCLR Reset path. The filter will detect and

ignore small pulses.

FIGURE 3-1:

RESET

Instruction

Stack

Pointer

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

Stack Full/Underflow Reset

External Reset

MCLR

VDD

SLEEP

WDT WDT

Module Time-out

Reset

VDD Rise

Detect

Power-on Reset

Brown-out

Reset BOREN

OSC1

OST/PWRT

OST

10-bit Ripple Counter

S

Chip_Reset

R

Q

PWRT

On-chip

Internal Osc(1)

10-bit Ripple Counter

Enable PWRT

Enable OST(2)

Note 1: This is a separate oscillator from the internal oscillator of the CLKIN pin.

2: See Table 3-1 for time-out situations.

 2001 Microchip Technology Inc.

Preliminary

DS41142A-page 15

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