KM4200 データシートの表示（PDF） - Fairchild Semiconductor
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KM4200 Datasheet PDF : 11 Pages
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DATA SHEET
Overdrive Recovery
Input
RL = 2kΩ
Vin =2Vpp
G=5
Rf = 1kΩ
Output
Time (20ns/div)
Figure 4: Overdrive Recovery
Driving Capacitive Loads
The Frequency Response vs. CL plot on page 4,
illustrates the response of the KM4200. A small series
resistance (Rs) at the output of the amplifier, illustrated
in Figure 5, will improve stability and settling
performance. Rs values in the Frequency Response vs.
CL plot were chosen to achieve maximum bandwidth
with less than 1dB of peaking. For maximum flatness,
use a larger Rs.
+
-
Rf
Rg
Rs
CL RL
KM4200
Refer to the evaluation board layouts shown in Figure
7 for more information.
When evaluating only one channel, complete the
following on the unused channel
1. Ground the non-inverting input
2. Short the output to the inverting input
Evaluation Board Information
The following evaluation boards are available to aid
in the testing and layout of this device:
Eval Board
KEB006
KEB010
Description
Dual Channel, Dual Supply
8 lead SOIC
Dual Channel, Dual Supply
8 lead MSOP
Products
KM4200IC8
KM4200IM8
Evaluation board schematics and layouts are shown in
Figure 6 and Figure 7.
The KEB006 evaluation board is built for dual supply
operation. Follow these steps to use the board in a
single supply application:
1. Short -Vs to ground
2. Use C3 and C4, if the -Vs pin of the KM4200 is
not directly connected to the ground plane.
Figure 5: Typical Topology for driving
a capacitive load
Layout Considerations
General layout and supply bypassing play major roles
in high frequency performance. Fairchild has evaluation
boards to use as a guide for high frequency layout
and to aid in device testing and characterization.
Follow the steps below as a basis for high frequency
layout:
s Include 6.8µF and 0.01µF ceramic capacitors
s Place the 6.8µF capacitor within 0.75 inches
of the power pin
s Place the 0.01µF capacitor within 0.1 inches
of the power pin
s Remove the ground plane under and around the
part, especially near the input and output pins to
reduce parasitic capacitance
s Minimize all trace lengths to reduce
series inductances
Figure 6: Evaluation Board Schematic
8
REV. 1A February 2001
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