28F004S3 データシートの表示（PDF） - Intel
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28F004S3 Datasheet PDF : 41 Pages
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E
28F004S3/28F008S3/28F016S3
Start
Write 20H,
Block Address
Write D0H,
Block Address
Read Status
Register
0
SR.7 =
1
Full Status
Check if Desired
Bus
Operation
Write
Command
Erase Setup
Write
Erase
Confirm
Comments
Data = 20H
Addr = Within Block to Be Erased
Data = D0H
Addr = Within Block to Be Erased
Read
Status Register Data
Suspend Block
Erase Loop
No
Suspend
Block Erase
Yes
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent block erasures.
Full status check can be done after each block erase, or after a
sequence of block erasures.
Write FFH after the last operation to place device in read array mode.
Block Erase
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
SR.3 = 1
0
VPP Range Error
1
SR.1 =
Device Protect Error
0
1
SR.4,5 =
0
Command Sequence
Error
1
SR.5 =
0
Block Erase
Successful
Block Erase
Error
Bus
Operation
Standby
Standby
Standby
Standby
Command
Comments
Check SR.3
1 = VPP Error Detect
Check SR.1
1 = Device Protect Detect
RP# = VIH , Block Lock-Bit Is Set
Only required for systems
implementing lock-bit configuration
Check SR.4,5
Both 1 = Command Sequence Error
Check SR.5
1 = Block Erase Error
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command in cases where multiple blocks are erased
before full status is checked.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
Figure 7. Automated Block Erase Flowchart
PRELIMINARY
21
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