11250-11 データシートの表示（PDF） - Conexant Systems

部品番号

コンポーネント説明

メーカー

11250-11

SmartHSF™ Mobile Modem

Conexant Systems 

Label

SDXTAL1

SDXTAL2

VDD

GND

VIO

LP_CLK

PLLVDD

PLLGND

SCANEN

SCANMODE

CLKRUN#

VpciDET

VauxDET

VpciEN#

VauxEN#

SROMCLK

SROMCS

SROMIN

SROMOUT

SmartHSF Mobile Modem Data Sheet

Pin

74

75

7, 18, 31, 47,

58, 68, 94

11, 36, 63, 89

22, 26

84

97

98

72

73

86

71

80

69

70

79

76

78

77

Table 3-2. CX11250 HSD Pin Signal Definitions

I/O I/O Type

Signal Name/Description

SYSTEM

I

Ix

O

Ox

Crystal/Clock In and Crystal Out. Connect SDXTAL1 to a 28.224000 MHz

crystal or clock circuit. Connect SDXTAL2 to the 28.224000 MHz crystal circuit

or leave open if SDXTAL1 is connected to a clock circuit.

P

PWR

Digital Supply Voltage. Connect to +3.3V.

G

GND

Digital Ground. Connect to digital ground.

P

PWR

I/O Signaling Voltage Reference. Connect to PCI Bus VI/O or +3.3V. Used

internally for PCI clamping.

RC

Low Power Clock RC Circuit. Connect to +3.3V through 240 KΩ.

P

PWR

Digital Supply Voltage. Connect to +3.3V and to GND through 0.1 µF.

G

GND

Digital Ground. Connect to digital ground.

I

Itpd

Scan Enable. Connect to GND.

I

Itpd

Scan Mode. Connect to GND.

I

I/Opod, Clock Running. CLKRUN# is an input used to determine the status of CLK

(o/d)

and an open drain output used to request starting or speeding up CLK.

Connect to GND for PCI Bus designs. Connect to CLKRUN# pin for Mini PCI

designs.

POWER DETECTION

I

Itpd

Vpci Detect. The VpciDET input indicates when PCI cycles and PCIRST# are

to be ignored. Connect this pin to the PCI Bus +5V pins for PCI Bus designs or

to PCI 3.3V for Mini PCI designs. VpciDET is deasserted when the PCI Bus

enters the B3 state.

This pin may alternatively be directly driven in embedded designs by using a

logical signal, either +5V or +3.3V level, to indicate when the PCI Bus is in a

B3 state. Driving this pin low synchronously to the PCI clock or when the PCI

clock is stopped also allows the HSD to be put into a very low power mode.

Using this method, if modem operation is not required, modem power

consumption can be reduced even while the PCI Bus is in power state B0.

I

Itpd

Vaux Detect. Active high input used to detect the presence of Vaux. Connect

to PCI Bus: Vaux. At device power on (POR), if D3_Cold bit in the EEPROM is

a 1, PMC[15] is set to a 1 if VauxDET is high or PMC[15] is cleared to a 0 if

VauxDET is low.

O

Ot2

Vpci Enable. Active low output used to enable Vpci FET. For use in designs

that switch between Vaux and Vpci for different power states and for retail

designs where the target PC may or may not support Vaux.

O

Ot2

Vaux Enable. Active low output used to enable Vaux FET. For use in designs

that switch between Vaux and Vpci for different power states and for retail

designs where the target PC may or may not support Vaux.

SERIAL EEPROM INTERFACE

O

Ot2

Serial ROM Shift Clock. Connect to SROM SK input (frequency: 537.6 kHz).

O

Ot2

Serial ROM Chip Select. Connect to SROM CS input.

I

Itpu

Serial ROM Device Status and Data Out. Connect to SROM DO output,

through 1 kΩ if using a +5V EEPROM.

O

Ot2

Serial ROM Instruction, Address, and Data In. Connect to SROM DI input.

100553B

Conexant

3-9

Share Link: