MX805AP データシートの表示（PDF） - MX-COM Inc
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MX805AP Datasheet PDF : 24 Pages
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Sub-Audio Signaling Processor
5
2 Signal List
MX805A
Pin
Signal
1 Xtal
2 Xtal/Clock
3 Address Select
4 IRQ
5 Serial Clock
6 Command Data
7 CS
8 Reply Data
9 TX Sub-Audio Out
10 Audio In
11 Audio Out
12 VSS
13 RX Amp In (-)
14 RX Amp In (+)
15 RX Amp Out
16 RX Sub-Audio In
17 RX Sub-Audio Out
18 VBIAS
19 Comparator In (-)
20 Comparator In (+)
Description
The output from the on-chip clock oscillator inverter. External components are
required at this input when a Xtal input is used. See Figure 2.
The input to the clock oscillator inverter. A Xtal or externally derived clock should
be connected here.
This input enables two MX805A’s to be used on the same C-BUS to provide dull-
duplex operation. See Table 4 and Table 5.
Interrupt Request . The output of this pin indicates an interrupt condition to the
microcontroller by going to a logic ‘0”. This ‘wire-or-able’ output allows the
connection of up to 8 peripherals to 1 interrupt port on the microcontroller. This
pin has a low impedance pulldown to logic ‘0’ when active, and a high impedance
when inactive. The system IRQ line requires 1 pull-up resistor to VDD. The
conditions that cause interrupts are indicated in the Table 5 and Table 7.
This is the ‘C-BUS’ serial Clock input. This clock, produced by the
microcontroller, is used for transfer timing of commands and data to and from the
MX805A. See timing diagrams.
This is the ‘C-BUS’ serial data input from the microcontroller. Data is loaded to
this device in 8-bit bytes, MSB (bit 7) first and LSB (bit 0) last, synchronized to the
Serial Clock. See Timing diagrams.
Chip Select . This is the ‘C-BUS’ data loading control function. This input is
provided by the microcontroller. Data transfer sequences are initiated, completed
or aborted by the CS signal. See Timing diagrams.
This is the ‘C-BUS’ serial data output to the microcontroller. The transmission of
Reply Data bytes is synchronized to the Serial Clock under the control of the CS
input. This 3-state output is held at high impedance when not sending data to the
microcontroller. See Timing Diagrams
This is the subaudio output (pure or NRZ derived). Signals are band limited. The
TX Output Filter had a variable bandwidth (See Table 9). This output is at VBIAS
(a) when the NRZ Encoder is enabled but no data is being transmitted, (b) when
the MX805A is placed in the Powersave All condition.
This is the input to the switched sub-audio bandstop (highpass) filter. It is
internally biased, and should be AC coupled by capacitor C7.
This is the output of the audio signal path (filter or bandpass). It is controlled by
the Control Register. When disabled, the pin is held at VBIAS.
Negative Supply (GND)
This is the inverting input to the on-chip RX Input Amp. (See Figure 2, Figure 3,
and Figure 4).
This is the non-inverting input to the on-chip RX Input Amp.
This is the output of the on-chip RX Input Op-Amp. This circuit may be used, with
external components, as a signal amplifier and anti-aliasing filter prior to the RX
Lowpass Filter, or for other purposes. See Figure 2 for Component details.
This is the received Sub-Audio (CTCSS/NRZ) input. It is internally referenced to
VBIAS. This signal to this pin should be AC coupled or biased. See Figure 2.
This is the output of the RX lowpass filter. It may be coupled into the on-chip
amplifier or comparator as required.
The internal circuitry bias line, held at VDD/2. This pin must be decoupled to VSS
by capacitor C8. See Figure 2.
This is the inverting input to the on-chip ‘comparator’ amplifier. See Figure 2,
Figure 3, and Figure 4.
This is the non-inverting input to the on-chip ‘comparator’ amplifier. See Figure 2,
Figure 3, and Figure 4.
1998 MX-COM, Inc.
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480116.004
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
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