PM4541 データシートの表示（PDF） - PMC-Sierra

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PM4541

T1XC EVALUATION DAUGHTER BOARD

PMC-Sierra 

TELECOM STANDARD PRODUCT

PMC-920314

ISSUE 2

PMC-Sierra, Inc.

PM4541 T1XC-EVBD

T1XC EVALUATION DAUGHTERBOARD

READ CYCLE

WRITE CYCLE

BALE

BE_CLOCK

BRWB

BA[15:8]

BAD[7:0]

BA="C0";

BRWB=1

BA °"C0";

BRWB=1

BA="C0";

BRWB=0

A[7:0] DOUT A[7:0] DOUT A[7:0]

DIN

BA °"C0";

BRWB=0

A[7:0]

DIN

T1XC_RDB

HCT245 DIR

T1XC_WRB

T1XC_CSB

Figure 4: Decode Logic Waveforms

6.3 Clock PLL and DIP Switches

One Mitel MT8940 provides all clocks necessary to drive the various backplane

rates supported by the T1XC. The MT8940 is a dual digital PLL which can provide

timing and synchronization signals for T1 or CEPT transmission links and the ST-

BUS . The first PLL provides the T1 clock (1.544 MHz) synchronized to an input

framing pulse. The second PLL provides CEPT or ST-BUS timing signals

synchronized to an internal or external framing pulse signal. For a more detailed

description of the device, refer to the datasheet on the MT8940 in the Mitel

Semiconductor Databook.

All outputs of the MT8940 are either brought out to header blocks or routed to the

CSU connector DIP sockets. A single 8-position DIP switch provides control over the

mode of the MT8940 device as well as control over the output clock enables. If the

MT8940 is not used, it can be removed from the daughterboard and its oscillators

can be replaced with 1.544 MHz and 2.048 MHz devices. The PLL oscillator clock

outputs are conveniently brought out to the header strip for use on the

daughterboard.

The mapping of the DIP switches to the MT8940 ports is as follows:

18

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