SAA7780 データシートの表示（PDF） - Philips Electronics
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コンポーネント説明
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SAA7780 Datasheet PDF : 70 Pages
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Philips Semiconductors
ThunderBird Q3D PCI Audio
Accelerator
Product Specification
SAA7780
Bit
7:0
Name
LATIME
R/W
RO
Function
The primary bus latency timer specifies the number of primary clocks that the
primary master may consume. It is set to zero since the joystick is a target
only.
Header Type Register - HEADER (RO)
PCI CFG 1
D7
D6
D5
D4
D3
D2
D1
D0
Offset 0Eh
MULTI_
FN
HEADER[6:0]
POR Value
1
0
0
0
0
0
0
0
Bit
7
6:0
Name
MULTI_FN
HEADER
R/W
RO
RO
Function
For the SAA7780, function 1, this bit has no meaning.
Header Type. A 00h indicates this device is not a PCI-to-PCI bridge.
BIST Register - BIST (RO)
PCI CFG 1
D7
D6
D5
D4
D3
D2
D1
D0
Offset 0Fh
BIST
START
R
R
CODE[3:0]
POR Value
0
0
0
0
0
0
0
0
Bit
7
Name
BIST
6
START
5:4 R
3:0 CODE
R/W
RO
RO
RO
RO
Function
BIST capable. BIST is not supported in the SAA7780, function 1 at this
revision.
If BIST capable, this bit will start the BIST. Writing a 1 will start the test and
the BIST should write this bit to a zero when complete. Software should fail
the device if the BIST is not complete after 2 seconds.
Reserved. These bits always return zero.
Completion Code. A value of zero means the device has passed its test.
Non-zero values means the device has failed using device specific failure
codes.
SAA7780 CFG Space 1 Legacy Base Address Registers
The SAA7780, contains one legacy I/O base registers in configuration space 1. The joystick is the sole legacy I/O base
address register and is documented here.
1999 Sep 30
51
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