CXD2450R データシートの表示（PDF） - Sony Semiconductor

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CXD2450R

Timing Generator for Progressive Scan CCD Image Sensor

Sony Semiconductor 

CXD2450R

D54 CLPSEL

0: XCPOB generation is stopped.

1: XCPOB is generated.

When generation is stopped, operation is the same as for D52 SSGSEL.

D55 IDSEL

0: ID generation is stopped.

1: ID is generated.

When generation is stopped, operation is the same as for D52 SSGSEL.

D56 HMCKSEL

0: 1/2MCK generation is stopped.

1: 1/2MCK is generated.

When generation is stopped, operation is the same as for D52 SSGSEL.

D57 TMCKSEL

0: 3/2MCK is generated.

1: 3/2MCK generation is stopped.

When generation is stopped, operation is the same as for D52 SSGSEL.

D58 HMCKREV

0: 1/2MCK reset when positive polarity.

1: 1/2MCK reset when negative polarity.

D59 HMCKREV

0: 3/2MCK reset when negative polarity.

1: 3/2MCK reset when positive polarity.

D60 to D61 DSG

The CXD2450R can apply stop control to the CCD pulses and pulses for the sample-and-hold and

analog/digital conversion ICs by setting the DSGAT pin low. Conversely, when the DSGAT pin is set high, the

controlled pulses can be switched as follows using the serial interface data.

D61 D60

Operating mode

0

0 No control performed

0

1 CCD pulse stop control

1

0 Sample-and-hold and analog/digital conversion IC pulse stop control

1

1 CCD pulse and sample-and-hold and analog/digital conversion IC pulse stop control

Here, CCD pulses refer to the H1, H2, RG, V1, V2a, V2b, V3 and VSUB pulses. Sample-and-hold and

analog/digital conversion IC pulses refer to the XSHP, XSHD, XRS, PBLK, XCLPOB, XCLPDM and CLD pulses.

See 7) Output timing characteristics using DSGAT of "AC Characteristics" for the stop control status of each pulse.

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