UT82CRH51AC-36WCX データシートの表示（PDF） - Aeroflex UTMC

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UT82CRH51AC-36WCX

UT82CRH51A USART

Aeroflex UTMC 

Standard Products

UT82CRH51A USART

Preliminary Data Sheet

December 9, 1999

FEATURES

q Synchronous and asynchronous operation

q Synchronous 5-8 bit characters; internal or external

character synchronization; automatic synchronization

insertion

q Asynchronous 5-8 bit characters; Clock Rate - 1, 16,

or 64 Times Baud Rate; break character generation; 1,

1.5, or 2 stop bits; false start bit detection; automatic

break detect and handling

q Synchronous baud rate - 1 to 64K baud

q Asynchronous baud rate - 1 to 19.2K baud

q Full-Duplex, double-buffered transmitter and receiver

q Error detection - parity, overrun and framing errors

q Radiation-hardened process and design; total dose

iradiation testing to MIL-STD-883 Method 1019

- Total-dose: 300 krad(Si)

- SEL LET threshold: greater than 120MeV-cm2/mg

- Neutron Fluence: 3.0E14n/cm2

q Packaging options:

- 36-lead Flatpack

- 68-lead Flatpack

q 5.0 and 3.3 volt operation

q Standard Microcircuit Drawing 5962-00505

- QML Q and V compliant part

q Available as core IP for ASIC applications

INTRODUCTION

The UT82CRH51A is an enhanced version of the industry

standard, Universal Synchronous/Asynchronous Receiver

Transmitter (USART), designed to provide data

communications between subsystem. The UT82CRH51A

USART is built using UTMC’s Commercial RadHardTM

epitaxial CMOS technology and is ideal for space applications.

In a communication environment an interface device converts

parallel format system data into serial format for transmission,

and converts incoming serial format data into parallel system

data for reception. The UT82CRH51A is used as a peripheral

device and is programmed by a host CPU to operate using

virtually any serial data transmission technique. The USART

accepts data characters from the CPU in a parallel format and

then converts the data into a continuous serial data stream for

transmission. Simultaneously, the UT82CRH51A receives

serial data streams and converts the data into a parallel data

character for the host CPU. The USART signals the CPU

whenever it accepts a new character for transmission or

whenever it has received a character for the CPU. The CPU

reads the complete status of the USART at any time. These

include data transmission errors and control signals such as

SYNDET/BRKDET, TxEMPTY.

D(7:0)

RESET

CLK

C/D

RD

WR

CS

DSR

DTR

CTS

RTS

DATA

BUS

BUFFER

TRANSMIT

BUFFER

(P-S)

READ/WRITE

CONTROL

LOGIC

TRANSMITTER

CONTROL

MODEM

CONTROL

INTERNAL

DATA BUS

RECEIVE

BUFFER

(S-P)

RECEIVER

CONTROL

Figure 1. UT82CRH51A USART Block Diagram

TxD

TxRDY

TxEMPTY

TxC

RxD

RxRDY

RxC

SYNDET/

BRKDET

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