UT82CRH51AC-36WCX データシートの表示（PDF） - Aeroflex UTMC
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UT82CRH51AC-36WCX Datasheet PDF : 26 Pages
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VSS
1
VDD
2
RxD
3
D4
4
NC
5
NC
6
D5
7
D6
8
D7
9
TxC
10
WR
11
CS
12
C/D
13
RD
14
RxRDY
15
D3
16
VDD
17
VSS
18
36
VSS
35
VDD
34
D2
33
D1
32
D0
31
RxC
30
DTR
29
RTS
28
DSR
27
RESET
26
CLK
25
TxD
24
TxEMPTY
23
CTS
22
SYNDET
21
TxRDY
20
VDD
19
VSS
Figure 2. UT82CRH51A Pinout (36)
NC
NC
C/D
NC
RD
NC
RxDY
NC
TxRDY
NC
SYNDET
NC
CTS
NC
TxE
NC
NC
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
27
9
28
8
29
7
30
6
31
5
32
4
33
3
34
Top View
2
35
1
36
68
37
67
38
66
39
65
40
64
41
63
42
62
43
61
44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Figure 3. UT82CRH51A Pinout (68)
1.0 Functional Description
The UT82CRH51A is designed for a wide range of
microcomputers. Like other I/O devices in a microcomputer
system, its functional configuration is programmed by the
system’s software for maximum flexibility. The UT82CRH51A
can support most serial data techniques in use.
In a communication environment an interface device must
convert parallel format system data into serial format for
transmission and convert incoming serial format data into
parallel system data for reception. The interface device must also
delete or insert bits or characters that are functionally unique to
the communication technique. Therefore, the interface should
appear "transparent" to the CPU, a simple input or output of byte-
oriented system data (figure 7).
1.1 DATA BUS BUFFER
This three-state, bidirectional, 8-bit buffer is used to interface the
UT82CRH51A to the system Data Bus. Data is transmitted or
received by the buffer upon execution of INput or OUTput
instructions of the CPU. Control words, Command words and
Status information are also transferred through the Data Bus
Buffer. The Command Status, Data-In and Data-Out registers
are separate, 8-bit registers communicating with the system bus
through the Data Bus Buffer.
This functional block accepts inputs from the system Control bus
NC and generates control signals for overall device operation. It
NC contains the Control Word Register and Command Word
VSS Register that store the various control formats for the device
NC
RxD functional definition.
NC 1.2 READ/WRITE CONTROL LOGIC
D3
NC 1.2.1 RESET (Reset)
D2
NC A "high" on this input forces the UT82CRH51A into an "Idle"
D1 mode. The device remains at "Idle" until a new set of control
NC words is written into the UT82CRH51A to program its function-
D0 al definition. Minimum RESET pulse width is 6tCY (clock must
NC be running).
VDD
NC A command reset operation also puts the device into the "Idle"
NC state.
1.2.2 CLK (CLOCK)
The CLK input is used to generate internal device timing and is
normally connected to the Phase 2 (TTL) output of the Clock
Generator. No external inputs or outputs are referenced to CLK,
but the frequency of CLK must be greater than 30 times the Re-
ceiver or Transmitter data bit rates.
1.2.3 WR (Write)
A "low" on this input informs the UT82CRH51A the CPU is
writing data or control words to the UT82CRH51A (figure 4).
2
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