UT82CRH51AC-36WCX データシートの表示（PDF） - Aeroflex UTMC

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UT82CRH51AC-36WCX

UT82CRH51A USART

Aeroflex UTMC 

RxC.

NOTE: In most communications systems, the UT82CRH51A

handles both the transmission and reception operations of a sin-

gle link. Consequently, the Receive and Transmit Baud Rates

will be the same. Both TxC and RxC requires identical frequen-

cies for this operation and can be tied together and connected to

a single frequency source (Baud Rate Generator) to simplify the

interface.

D(7:0)

DATA

BUS

BUFFER

TRANSMIT

BUFFER

TxD

(P-S)

RESET

CLK

C/D

RD

WR

CS

DSR

DTR

CTS

RTS

READ/WRITE

CONTROL

LOGIC

MODEM

CONTROL

INTERNAL

DATA BUS

TRANS-

MITTER

CONTROL

RECEIVER

BUFFER

(S-P)

RECEIVER

CONTROL

TxRDY

TxEMPTY

TxC

RxD

RxRDY

RxC

SYNDET/

BRKDET

Figure 6. UT82CRH51A Block Diagram Showing

Receiver Buffer and Control Functions

When used as an input (external SYNC detect mode), a positive

going signal causes the UT82CRH51A to start assembling data

characters on the rising edge of the next RxC. Once in SYNC,

the "high" input signal can be removed. When External SYNC

Detect is programmed, Internal SYNC Detect is disabled.

1.7.4 BREAK (Async Mode Only)

This output goes high whenever the receiver remains low

through two consecutive stop bit sequences (including the start

bits, data bits, and parity bits). Break Detect may also be read

as a Status bit. It is reset only upon a master chip Reset or Rx

Data returning to a "one" state.

ADDRESS BUS

A0

CONTROL BUS

I/O R I/O W RESET

DATA BUS

02

(TTL)

8

1.7.3 SYNDET (SYNC Detect/BRKDET Break Detect)

This pin is used in Synchronous Mode for SYNDET and may be

used as either input or output programmable through the Control

Word. It is reset to output mode low upon RESET. When used

as an output (internal Sync mode), the SYNDET pin goes high

to indicate that the UT82CRH51A has located the SYNC char-

acter in the Receive mode. If the UT82CRH51A is programmed

to use double Sync characters (bisync), then SYNDET goes high

in the middle of the last bit of the second Sync character. SYN-

DET automatically resets upon a Status Read Operation.

C/D CS

D7-D0

RD WR RESET CLK

UT82CRH51A

Figure 7. UT82CRH51A Interface to Standard

System Bus

5

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