UT82CRH51AC-36WCX データシートの表示（PDF） - Aeroflex UTMC

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UT82CRH51AC-36WCX

UT82CRH51A USART

Aeroflex UTMC 

2.0 DETAILED OPERATION DESCRIPTION

2.1 General

The complete functional definition of the UT82CRH51A is pro-

grammed by the system’s software. A set of control words must

be sent out by the CPU to initialize the UT82CRH51A to sup-

port the desired communications format. These control words

will program the: BAUD RATE, CHARACTER LENGTH,

NUMBER OF STOP BITS, SYNCHRONOUS or ASYN-

CHRONOUS OPERATION, EVEN/ODD/OFF PARITY, etc.

In the Synchronous Mode, options are also provided to select ei-

ther internal or external character synchronization (figure 8).

Once programmed, the UT82CRH51A is ready to perform its

communication functions. The TxRDY output is raised "high"

to signal the CPU the UT82CRH51A is ready to receive a data

character from the CPU. This output (TxRDY) is reset automat-

ically when the CPU writes a character into the UT82CRH51A.

On the other hand, the UT82CRH51A receives serial data from

the MODEM or I/O device. Upon receiving an entire character,

the RxRDY output is raised "high" to signal the CPU the

UT82CRH51A has completed character ready for the CPU to

fetch. RxRDY is reset automatically upon the CPU data read

operation.

The UT82CRH51A cannot begin transmission until the TxEn-

able (Transmitter Enable) bit is set in the Command Instruction

and it has received a Clear to Send ( CTS) input. The TxD output

is held in the marking state upon Reset.

C/D = 1

C/D = 1

C/D = 1

C/D = 1

MODE INSTRUCTION

SYNC CHARACTER 1

SYNC CHARACTER 2

COMMAND INSTRUCTION

SYNC

MODE

ONLY*

C/D = 0

DATA

C/D = 1

COMMAND INSTRUCTION

C/D = 0

DATA

C/D = 1

COMMAND INSTRUCTION

NOTE: The second SYNC character is skipped if MODE instruction has programmed

the UT82CRH51A to single character internal SYNC Mode. Both SYNC characters are

skipped if MODE instruction has programmed the UT82CRH51A to ASYNC mode or

External SYNC mode.

Figure 8. Typical Data Block

2.2 Programming the UT82CRH51A

Prior to starting data transmission or reception, the

UT82CRH51A must be loaded with a set of control words gen-

erated by the CPU. These control signals define the complete

functional definition of the UT82CRH51A and must immediate-

ly follow a Reset operation (internal or external).

The control words are split into two formats:

1. Mode Instruction

2. Command Instruction

2.2.1 Mode Instruction

This instruction defines the general operational characteristics

of the UT82CRH51A. It must follow a Reset operation (internal

or external), once the Mode Instruction has been written into the

UT92CRH51A by the CPU, SYNC characters or Command In-

structions (figure 8).

2.2.2 Command Instruction

This instruction defines a word that is used to control the actual

operation of the UT82CRH51A.

Both the Mode and Command Instructions must conform to a

specified sequence for proper device operation (see Figure 8).

The Mode Instruction must be written immediately following a

Reset operation prior to using the UT82CRH51A for data com-

munication.

All control words written into the UT82CRH51A after the Mode

Instruction loads the Command Instruction. Command Instruc-

tions can be written into the UT82CRH51A at any time in the

data block during the operation of the UT82CRH51A. To return

to the Mode Instruction format, the master Reset bit in the Com-

mand Instruction word can be set to initiate an internal Reset op-

eration which automatically places the UT82CRH51A back into

the Mode Instruction format. Command Instructions must fol-

low the Mode Instructions or Sync characters.

2.2.3 Mode Instruction Definition

The UT82CRH51A can be used for either Asynchronous or

Synchronous data communication. To understand how the

Mode Instruction defines the functional operation of the

UT82CRH51A, the designer views the device as two separate

components, one Asynchronous and the other Synchronous,

sharing the same package. The format definition can be

changed only after a master chip Reset. For explanation purpos-

es the two formats will be isolated.

NOTE: When parity is enabled it is not considered as one of the

data bits for the purpose of programming the word length. The

actual parity bit received on the Rx Data line cannot be read on

the Data bus. In the case of a programmed character length of

less than 8 bits, the least significant Data Bus bits holds the data;

unused bits are "don’t care" when writing data to the

UT82CRH51A and will be "zeroes" when reading the data from

the UT82CRH51A.

2.2.4 Asynchronous Mode (Transmission)

Whenever a data character is sent by the CPU the

UT82CRH51A automatically adds a Start bit (low level) fol-

lowed by the data bits (least significant bit first), and the pro-

grammed number of Stop bits to each character. Also, an even

or odd Parity bit is inserted prior to the Stop bit(s) as defined by

6

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