UT82CRH51AC-36WCX データシートの表示（PDF） - Aeroflex UTMC

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UT82CRH51AC-36WCX

UT82CRH51A USART

Aeroflex UTMC 

the Mode Instruction. The character is then transmitted as a se-

rial data stream on the TxD output. The serial data is shifted out

on the falling edge of TxC at a rate equal to 1, 1/16, or 1/64 that

of the TxC as defined by the Mode Instruction. BREAK char-

acters can be continuously sent to the TxD if commanded to do

so.

When no data characters have been loaded into the

UT82CRH51A the TxD output remains "high" (marking) unless

a Break (continuously low) has been programmed (figure 9).

D7 D6 D5 D4 D3 D2 D1 D0

S2 S1 EP PEN L2 L1 B2 B1

BAUD RATE FACTOR

0

0

SYNC

MODE

10

1

01

1

(1X) (16X) (64X)

CHARACTER LENGTH

0

0

5

BITS

10

1

01

1

6

7

8

BITS BITS BITS

PARITY ENABLE

1 = ENABLE 0 = DISABLE

EVEN PARITY

GENERATION/CHECK

1 = EVEN 0= ODD

NUMBER OF STOP BITS

0

1

0

0

INVALID 1

BITS

0

1

1

1 1/2

BITS

1

2

BITS

(ONLY AFFECTS Tx:Rx

NEVER REQUIRES MORE

THAN ONE STOP BIT)

Figure 9. Mode and Command Instruction Format,

Asynchronous Node

2.2.5 Asynchronous Mode (Receive)

The RxD line is normally high. A falling edge on this line trig-

gers the beginning of a START bit. The validity of this START

bit is checked by again strobing this bit at its nominal center

(16x or 64x mode only). If a low is detected again, it is a valid

START bit, and the bit counter starts counting. The bit counter

thus locates the center of the data bits, the parity bit (if it exists),

and the stop bits. If parity error occurs, the parity error flag is

set. Data and parity bits are sampled on the RxD pin with the

rising edge of RxC. If a low level is detected as the STOP bit,

the Framing Error flag sets. The STOP bit signals the end of a

character. Note: The receiver requires only one stop bit regard-

less of the number of stop bits programmed. This character is

then loaded into the parallel I/O buffer of the UT82CRH51A.

The RxRDY pin is raised to signal the CPU that a character is

ready to be fetched. If a previous character has not been fetched

by the CPU, the present character replaces it in the I/O buffer,

and the OVERRUN Error flag is raised (thus the previous char-

acter is lost). All of the error flags can be reset by an Error Reset

Instruction. The occurrence of any of these errors will not affect

the operation of the UT82CRH51A (figure 10).

2.2.6 Synchronous Mode (Transmission)

The TxD output is continuously high until the CPU sends its

first character to the UT82CRH51A which usually is a SYNC

character. When the CTS line goes low, the first character is se-

rially transmitted out. All characters are shifted out on the fall-

ing edge of TxC. Data is shifted out at the same rate as the TxC.

Once transmission has started, the data stream at TxD output

continues at the TxC rate. If the CPU does not provide the

UT82CRH51A with a data character before the UT82CRH51A

Transmitter Buffers become empty, the SYNC characters (or

character if in single SYNC character mode) will be automati-

cally inserted in the TxD data stream. In this case, the TxEMP-

TY pin is raised high to signal that the UT82CRH51A is empty

and SYNC characters are being sent out. TxEMPTY does not

go low when the SYNC is being shifted out (see figure 11). The

TxEMPTY pin is internally reset by a data character being writ-

ten into the UT82CRH51A.

AUTOMATICALLY INSERTED BY USART

TxD DATA DATA SYNC 1 SYNC 2 DATA - - - - - -

TxEMPTY

FALLS UPON CPU

WRITING A

CHARACTER TO

THE USART

NOMINAL CENTER OF LAST BIT

Figure 11. Synchronous Mode

7

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