AD7305BN データシートの表示（PDF） - Analog Devices

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AD7305BN

+3 V/+5 V, Rail-to-Rail Quad, 8-Bit DAC

Analog Devices 

AD7304/AD7305

AD7304 PIN FUNCTION DESCRIPTIONS

Pin # Name

Function

1

VOUTB

Channel B rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to VREFB pin. Output

is open circuit when SHDN is enabled.

2

VOUTA

Channel A rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to VREFA pin. Output

is open circuit when SHDN is enabled.

3

VSS

4

VREFA

5

VREFB

6

GND

7

LDAC

8

CLR

9

CS

10 CLK

Negative Power Supply Input. Specified range of operation 0 V to –5.5 V.

Channel A Reference Input. Establishes VOUTA full-scale voltage. Specified range of operation VSS < VREFA < VDD.

Channel B Reference Input. Establishes VOUTB full-scale voltage. Specified range of operation VSS < VREFB < VDD.

Common Analog and Digital Ground.

Load DAC register strobe, active low. Transfers all four Input Register data into their DAC registers. Asynchronous

active low input. DAC Register is transparent when LDAC = 0. See Control Logic Truth Table for operation.

Clears all Input and DAC registers to the zero condition. Asynchronous active low input. The serial register is not effected.

Chip Select, Active Low Input. Disables shift register loading when high. Transfers Serial Input Register Data to the

decoded Input Register when CS returns HIGH. Does not effect LDAC operation.

Clock input, positive edge clocks data into shift register. Disabled by chip select CS.

11 SDI/SHDN Serial Data-Input loads directly into the shift register, MSB first. Hardware shutdown (SHDN) control input, active

when pin is left floating by a three-state logic driver. Does not effect DAC register contents as long as power is

present on VDD.

12

VREFD

Channel D Reference Input. Establishes VOUTD full-scale voltage. Specified range of operation VSS < VREFD < VDD.

13

VREFC

Channel C Reference Input. Establishes VOUTC full-scale voltage. Specified range of operation VSS < VREFC < VDD.

14

VDD

Positive power supply input. Specified range of operation +2.7 V to +5.5 V.

15

VOUTD

Channel D rail-to-rail buffered DAC voltage output. Full-scale set by reference voltage applied to VREFD pin. Output

is open circuit when SHDN is enabled.

16

VOUTC

Channel C rail-to-rail buffered DAC voltage output. Full-scale set by reference voltage applied to VREFC pin. Output

is open circuit when SHDN is enabled.

Pin # Name

1

VOUTB

2

VOUTA

3

VSS

4

VREF

5

GND

6

LDAC

7

DB7

8

DB6

9

DB5

10 DB4

11 DB3

12 DB2

13 DB1

14 DB0

15 WR

16 A1

17 A0/SHDN

18

VDD

19

VOUTD

20

VOUTC

AD7305 PIN FUNCTION DESCRIPTIONS

Function

Channel B rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to VREFB pin. Output

is open circuit when SHDN is enabled.

Channel A rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to VREFA pin. Output

is open circuit when SHDN is enabled.

Negative Power Supply Input. Specified range of operation 0 V to –5.5 V.

Channel B Reference Input. Establishes VOUT full-scale voltage. Specified range of operation VSS < VREF < VDD.

Common Analog and Digital Ground.

Load DAC register strobe, active low. Transfers all four Input Register data into their DAC registers. Asynchronous

active low input. DAC Register is transparent when LDAC = 0. See Control Logic Truth Table for operation.

MSB Digital Input Data Bit.

Data Bit 6.

Data Bit 5.

Data Bit 4.

Data Bit 3.

Data Bit 2.

Data Bit 1.

LSB Digital Input Data Bit.

Write data into Input Register control line, active low. See Control Logic Truth Table for operation.

Address Bit 1.

Address Bit 0/Hardware shutdown (SHDN) control input, active when pin is left floating by a three-state logic driver.

Does not effect DAC register contents as long as power is present on VDD.

Positive Power Supply Input. Specified range of operation +2.7 V to +5.5 V.

Channel D rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to VREFD pin. Output

is open circuit when SHDN is enabled.

Channel C rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to VREFC pin. Output

is open circuit when SHDN is enabled.

–6–

REV. A

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