Q67100-H5164 データシートの表示（PDF） - Micronas
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Q67100-H5164 Datasheet PDF : 42 Pages
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SDA 5650/X
Preliminary Data Sheet
2.3 Order of Data Output on the I2C Bus and Bit Allocation of PDC/VPS
Operating Modes (cont’d)
I2C Bus
Byte 5
Byte 6
Byte 7
Byte 8
bit 7
6
5
4
3
2
1
0
bit 7
6
5
4
3
2
1
0
bit 7
6
5
4
3
2
1
0
bit 7
6
5
4
3
2
1
0
PDC Packet 8/30
Format 1
Format 2
byte 19
bit 0
1
2
3
4
5
6
7
byte 14
byte 15
bit 0
1
2
3
bit 0
1
2
3
byte 20
bit 0
1
2
3
4
5
6
7
byte 24
byte 25
bit 0
1
2
3
bit 0
1
2
3
byte 21
bit 0
1
2
3
4
5
6
7
byte 13 bit 0
1
2
3
– set to “1”
– set to “1”
– set to “1”
– set to “1”
byte 13
bit 0
1
2
3
4
5
6
7
VPS Mode
byte 5
bit 0
1
2
3
4
5
6
7
byte 15
bit 0
1
2
3
4
5
6
7
– set to “1”
– set to “1”
– set to “1”
– set to “1”
– set to “1”
– set to “1”
– set to “1”
– set to “1”
1) Message bit numbers according to EBU specification of PDC system.
2) Transmission bit number.
Micronas
12
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