AD9912A データシートの表示（PDF） - Analog Devices

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AD9912A

1 GSPS Direct Digital Synthesizer with 14-Bit DAC

Analog Devices 

Parameter

SYSTEM CLOCK INPUT

SYSCLK PLL Bypassed

Input Capacitance

Input Resistance

Internally Generated DC Bias Voltage2

Differential Input Voltage Swing

SYSCLK PLL Enabled

Input Capacitance

Input Resistance

Internally Generated DC Bias Voltage2

Differential Input Voltage Swing

Crystal Resonator with SYSCLK PLL Enabled

Motional Resistance

CLOCK OUTPUT DRIVERS

HSTL Output Driver

Differential Output Voltage Swing

Common-Mode Output Voltage2

CMOS Output Driver

Output Voltage High (VOH)

Output Voltage Low (VOL)

Output Voltage High (VOH)

Output Voltage Low (VOL)

TOTAL POWER DISSIPATION

DDS Only

Min Typ Max

1.5

2.4

2.6 2.9

0.93 1.17 1.38

632

3

2.4

2.6 2.9

0.93 1.17 1.38

632

9

100

1080 1280 1480

0.7

0.88 1.06

2.7

0.4

1.4

0.4

637 765

DDS with Spur Reduction On

DDS with HSTL Driver Enabled

DDS with CMOS Driver Enabled

686 823

657 788

729 875

DDS with HSTL and CMOS Drivers Enabled

747 897

DDS with SYSCLK PLL Enabled

Power-Down Mode

648 777

13 16

1 Pin 14 is in the AVDD3 group, but it is recommended that Pin 14 be tied to Pin 1.

2 AVSS = 0 V.

AD9912

Unit Test Conditions/Comments

System clock inputs should always be ac-

coupled (both single-ended and differential)

pF

kΩ

V

mV p-p

Single-ended, each pin

Differential

Equivalent to 316 mV swing on each leg

pF

kΩ

V

mV p-p

Single-ended, each pin

Differential

Equivalent to 316 mV swing on each leg

Ω

25 MHz, 3.2 mm × 2.5 mm AT cut

mV

Output driver static, see Figure 27 for

output swing vs. frequency

V

Output driver static, see Figure 28 and

Figure 29 for output swing vs. frequency

V

IOH = 1 mA, Pin 37 = 3.3 V

V

IOL = 1 mA, Pin 37 = 3.3 V

V

IOH = 1 mA, Pin 37 = 1.8 V

V

IOL = 1 mA, Pin 37 = 1.8 V

mW

Power-on default, except SYSCLK PLL by-

passed and CMOS driver off; SYSCLK = 1 GHz;

HSTL driver off; spur reduction off; fOUT =

200 MHz

mW

Same as “DDS Only” case, except both spur

reduction channels on

mW

Same as “DDS Only” case, except HSTL driver

enabled

mW

Same as “DDS Only” case, except CMOS

driver and S-divider enabled and at 3.3 V;

CMOS fOUT = 50 MHz (S-divider = 4)

mW

Same as “DDS Only” case, except both HSTL

and CMOS drivers enabled; S-divider

enabled and set to 4; CMOS fOUT = 50 MHz

mW

Same as “DDS Only” case, except 25 MHz on

SYCLK input and PLL multiplier = 40

mW

Using either the power-down and enable

register or the PWRDOWN pin

Rev. F | Page 5 of 40

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