AD9912ABCPZ データシートの表示（PDF） - Analog Devices
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AD9912ABCPZ Datasheet PDF : 40 Pages
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AD9912
AC SPECIFICATIONS
fS = 1 GHz, DAC RSET = 10 kΩ, unless otherwise noted. Power supply pins within the range specified in the DC Specifications section.
Table 2.
Parameter
Min
FDBK_IN INPUT
Input Frequency Range
10
Minimum Differential Input Level
225
40
SYSTEM CLOCK INPUT
SYSCLK PLL Bypassed
Input Frequency Range
250
Duty Cycle
45
Minimum Differential Input Level
632
SYSCLK PLL Enabled
VCO Frequency Range, Low Band
700
VCO Frequency Range, Auto Band
810
VCO Frequency Range, High Band
900
Maximum Input Rate of System
Clock PFD
Without SYSCLK PLL Doubler
Input Frequency Range
11
Multiplication Range
4
Minimum Differential Input Level 632
With SYSCLK PLL Doubler
Input Frequency Range
6
Multiplication Range
8
Input Duty Cycle
Minimum Differential Input Level 632
Crystal Resonator with SYSCLK PLL
Enabled
Crystal Resonator Frequency Range 10
Maximum Crystal Motional Resistance
CLOCK DRIVERS
HSTL Output Driver
Frequency Range
20
Duty Cycle
48
Rise Time/Fall Time (20% to 80%)
Jitter (12 kHz to 20 MHz)
HSTL Output Driver with 2× Multiplier
Frequency Range
400
Duty Cycle
45
Rise Time/Fall Time (20% to 80%)
Subharmonic Spur Level
Jitter (12 kHz to 20 MHz)
CMOS Output Driver
(AVDD3/Pin 37) @ 3.3 V
Frequency Range
0.008
Duty Cycle
45
Rise Time/Fall Time (20% to 80%)
Typ Max
400
Unit
MHz
mV p-p
V/μs
Test Conditions/Comments
Pin 40, Pin 41
−12 dBm into 50 Ω; must be ac-coupled
Pin 27, Pin 28
1000
55
MHz
%
mV p-p
Maximum fOUT is 0.4 × fSYSCLK
Equivalent to 316 mV swing on each leg
810
MHz
900
MHz
1000 MHz
200
MHz
When in the range, use the low VCO band exclusively
When in the range, use the VCO auto band select
When in the range, use the high VCO band exclusively
200
MHz
66
Integer multiples of 2, maximum PFD rate and system clock
frequency must be met
mV p-p Equivalent to 316 mV swing on each leg
100
MHz
132
Integer multiples of 8
50
%
Deviating from 50% duty cycle may adversely affect
spurious performance
mV p-p Equivalent to 316 mV swing on each leg
50
MHz
100
Ω
AT cut, fundamental mode resonator
See the SYSCLK Inputs section for recommendations
725
MHz
52
%
115 165
ps
1.5
ps
725
MHz
55
%
115 165
ps
−35
dBc
1.6
ps
See Figure 27 for maximum toggle rate
100 Ω termination across OUT/OUTB, 2 pF load
fOUT = 155.52 MHz, 50 MHz system clock input (see Figure 12
through Figure 14 for test conditions)
100 Ω termination across OUT/OUTB, 2 pF load
Without correction
fOUT = 622.08 MHz, 50 MHz system clock input (see Figure 15
for test conditions)
150
MHz
55
65
%
3
4.6
ns
See Figure 29 for maximum toggle rate; the S-divider
should be used for low frequencies because the FDBK_IN
minimum frequency is 10 MHz
With 20 pF load and up to 150 MHz
With 20 pF load
Rev. F | Page 6 of 40
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