AD9912A データシートの表示（PDF） - Analog Devices
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AD9912A Datasheet PDF : 40 Pages
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AD9912
Parameter
Min
Typ Max Unit
CMOS Output Driver
(AVDD3/Pin 37) @ 1.8 V
Frequency Range
0.008
40
MHz
Duty Cycle
45
55
65
%
Rise Time/Fall Time (20% to 80%)
5
6.8
ns
DAC OUTPUT CHARACTERISTICS
DCO Frequency Range (1st Nyquist Zone) 0
450
MHz
Output Resistance
Output Capacitance
Full-Scale Output Current
Gain Error
Output Offset
Voltage Compliance Range
Wideband SFDR
20.1 MHz Output
98.6 MHz Output
201.1 MHz Output
398.7 MHz Output
Narrow-Band SFDR
20.1 MHz Output
98.6 MHz Output
201.1 MHz Output
398.7 MHz Output
DIGITAL TIMING SPECIFICATIONS
Time Required to Enter Power-Down
Time Required to Leave Power-Down
Reset Assert to High-Z Time
for S1 to S4 Configuration Pins
SERIAL PORT TIMING SPECIFICATIONS
SCLK Clock Rate (1/tCLK )
50
Ω
5
pF
20
31.7 mA
−10
+10 % FS
0.6
μA
AVSS − +0.5 AVSS + V
0.50
0.50
−79
dBc
−67
dBc
−61
dBc
−59
dBc
−95
dBc
−96
dBc
−91
dBc
−86
dBc
15
μs
18
μs
60
ns
25
50
MHz
SCLK Pulse Width High, tHIGH
8
ns
SCLK Pulse Width Low, tLOW
8
ns
SDO/SDIO to SCLK Setup Time, tDS
1.93
ns
SDO/SDIO to SCLK Hold Time, tDH
1.9
ns
SCLK Falling Edge to Valid Data on
SDIO/SDO, tDV
11
ns
CSB to SCLK Setup Time, tS
1.34
ns
CSB to SCLK Hold Time, tH
−0.4
ns
CSB Minimum Pulse Width High, tPWH
3
ns
IO_UPDATE Pin Setup Time
tCLK
sec
(from SCLK Rising Edge of the Final Bit)
IO_UPDATE Pin Hold Time
tCLK
sec
PROPAGATION DELAY
FDBK_IN to HSTL Output Driver
2.8
ns
FDBK_IN to HSTL Output Driver with 2×
7.3
ns
Frequency Multiplier Enabled
FDBK_IN to CMOS Output Driver
8.0
ns
FDBK_IN Through S-Divider to CMOS
Output Driver
8.6
ns
Frequency Tuning Word Update:
IO_UPDATE Pin Rising Edge to DAC
Output
60/fS
ns
Test Conditions/Comments
See Figure 28 for maximum toggle rate
With 20 pF load and up to 40 MHz
With 20 pF load
DAC lower limit is 0 Hz; however, the minimum slew rate
for FDBK_IN dictates the lower limit if using CMOS or HSTL
outputs
Single-ended (each pin internally terminated to AVSS)
Range depends on DAC RSET resistor
Outputs connected to a transformer whose center tap is
grounded
See the Typical Performance Characteristics section
0 MHz to 500 MHz
0 MHz to 500 MHz
0 MHz to 500 MHz
0 MHz to 500 MHz
See the Typical Performance Characteristics section
±250 kHz
±250 kHz
±250 kHz
±250 kHz
Time from rising edge of RESET to high-Z on the S1, S2, S3,
S4 configuration pins
Refer to Figure 56 for all write-related serial port parameters;
maximum SCLK rate for readback is governed by tDV
Refer to Figure 54
tCLK = period of SCLK in Hz
tCLK = period of SCLK in Hz
S-divider bypassed
fS = system clock frequency in GHz
Rev. F | Page 7 of 40
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