ICS1893AG データシートの表示（PDF） - Integrated Circuit Systems
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ICS1893AG Datasheet PDF : 135 Pages
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ICS1893AG Data Sheet - Preliminary
Table of Contents
Table of Contents
Section
8.14
8.14.1
8.14.2
8.14.3
8.14.4
8.14.5
8.14.6
8.14.7
Chapter 9
9.1
9.2
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
Title
Page
Register 19: Extended Control Register 2 ............................................................. 96
Node/Repeater Configuration (bit 19.15) ............................................................... 97
Hardware/Software Priority Status (bit 19.14) ........................................................ 97
Remote Fault (bit 19.13) ........................................................................................ 97
ICS Reserved (bits 19.12:8) ................................................................................... 97
Twisted Pair Tri-State Enable, TPTRI (bit 19.7) ..................................................... 97
ICS Reserved (bits 19.6:1) ..................................................................................... 97
Automatic 100Base-TX Power-Down (bit 19.0) ..................................................... 97
Pin Diagram, Listings, and Descriptions ....................................................................... 98
ICS1893AG Pin Diagram ....................................................................................... 98
ICS1893AG Pin Descriptions ................................................................................. 99
Transformer Interface Pins ...................................................................................100
Multi-Function (Multiplexed) Pins: PHY Address and LED Pins ...........................101
Configuration Pins.................................................................................................104
MAC Interface Pins ...............................................................................................105
Ground and Power Pins........................................................................................109
Chapter 10
10.1
10.2
10.3
10.4
10.4.1
10.4.2
10.4.3
10.4.4
10.5
10.5.1
10.5.2
10.5.3
10.5.4
10.5.5
10.5.6
10.5.7
10.5.8
10.5.9
10.5.10
10.5.11
10.5.12
10.5.13
DC and AC Operating Conditions............................................................................... 110
Absolute Maximum Ratings .................................................................................110
Recommended Operating Conditions ..................................................................110
Recommended Component Values .....................................................................111
DC Operating Characteristics ..............................................................................112
DC Operating Characteristics for Supply Current ................................................112
DC Operating Characteristics for TTL Inputs and Outputs ..................................112
DC Operating Characteristics for REF_IN ...........................................................113
DC Operating Characteristics for Media Independent Interface ..........................113
Timing Diagrams ..................................................................................................114
Timing for Clock Reference In (REF_IN) Pin .......................................................114
Timing for Transmit Clock (TXCLK) Pins .............................................................115
Timing for Receive Clock (RXCLK) Pins ..............................................................116
100M MII: Synchronous Transmit Timing .............................................................117
10M MII: Synchronous Transmit Timing ..............................................................118
100M/MII Media Independent Interface: Synchronous Receive Timing ...............119
MII Management Interface Timing .......................................................................120
10M Media Independent Interface: Receive Latency ...........................................121
10M Media Independent Interface: Transmit Latency...........................................122
100M/MII Media Independent Interface: Transmit Latency...................................123
100M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission)................124
10M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission)..................125
100M MII Media Independent Interface: Receive Latency....................................126
ICS1893AG, Rev. A 04/14/05
Copyright © 2005, Integrated Circuit Systems, Inc.
All rights reserved.
7
April, 2005
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