TDA936X データシートの表示（PDF） - Philips Electronics
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TDA936X Datasheet PDF : 140 Pages
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Philips Semiconductors
TV signal processor-Teletext decoder with
embedded µ-Controller
Preliminary specification
TDA 935X/6X/8X series
7FH
2FH
Bank Select
Bits in PSW
20H
1FH
11 = BANK3
18H
17H
10 = BANK2
10H
01 = BANK1 0FH
08H
07H
00 = BANK0
00H
Bit Addressable Space
(Bit Addresses 0-7F)
4 Banks of
8 Registers
R0 - R7
Figure 10 Lower 128 Bytes of Internal RAM
The upper 128 bytes is not allocated for any special area or functions.
SFR Memory
The Special Function Register (SFR) space is used for Port latches, timer, peripheral control, acquisition control,
display control, etc. These register can only be accessed by direct addressing. Sixteen of the addresses in the
SFR space are both byte and bit-addressable. The bit-addressable SFR’s are those whose address ends in 0H
or 8H. A summary of the SFR map in address order is shown in Table 3..
ADD R/W
Names
80H
R/W P0
81H
R/W SP
82H
R/W DPL
83H
R/W DPH
87H
R/W PCON
88H
R/W TCON
89H
R/W TMOD
8AH
R/W TL0
8BH
R/W TL1
BIT7
-
SP<7>
DPL<7>
DPH<7>
0
TF1
GATE
TL0<7>
TL1<7>
BIT6
BIT5
BIT4
P0<6>
P0<5>
-
SP<6>
SP<5>
SP<4>
DPL<6>
DPL<5>
DPL<4>
DPH<6>
DPH<5>
DPH<4>
ARD
RFI
WLE
TR1
TF0
TR0
C/T
M1
M0
TL0<6>
TL0<5>
TL0<4>
TL1<6>
TL1<5>
TL1<4>
Table 3 SFR Map
BIT3
-
SP<3>
DPL<3>
DPH<3>
GF1
IE1
GATE
TL0<3>
TL1<3>
BIT2
-
SP<2>
DPL<2>
DPH<2>
GF0
IT1
C/T
TL0<2>
TL1<2>
BIT1
-
SP<1>
DPL<1>
DPH<1>
PD
IE0
M1
TL0<1>
TL1<1>
BIT0
-
SP<0>
DPL<0>
DPH<0>
IDL
IT0
M0
TL0<0>
TL1<0>
1999 Sep 28
15
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